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Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis

Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. Nicholas Imbriglia, Nuno Alves, Elif Alpaslan, Jennifer Dworak Brown University NATW 2010. Motivation. As electronic devices become smaller, they become more and more susceptible to wearout and latent defects:

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Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis

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  1. Dynamic Test Set Selection Using Implication-BasedOn-Chip Diagnosis Nicholas Imbriglia, Nuno Alves, Elif Alpaslan, Jennifer Dworak Brown University NATW 2010

  2. Motivation • As electronic devices become smaller, they become more and more susceptible to wearout and latent defects: • Time Dependent Dielectric Breakdown (TDDB) • Negative Bias Temperature Instability (NBTI) • Electromigration

  3. Motivation • This susceptibility is application and workload dependent • Large ramifications for the online testing of homogeneous, multi-core architectures • If a core fails, similar cores should be tested

  4. Our Solution • Efficient online error detection • Detect during normal circuit operation • Efficient online testing of homogeneous cores • Test sets short in length • Focus on a small area of the circuit • Multiple detects in this area

  5. Our Solution • We wish to use the diagnostic information inherent to logic implications to target specific sections of a device • We can then develop test sets specially suited for testing these sections online • These test sets, since they focus only on a portion of the device, can be very short and can be run with minimal interruption of the device’s normal operation

  6. Related Work • Online Error Detection • Triple Modular Redundancy • Berger and Bose Lin Coding • Logic Implications • Online Test • Concurrent Autonomous Chip Self-Test Using Stored Test Patterns (CASP)

  7. Logic Implications • Provide valuable diagnostic resolution • The checker hardware requires very little knowledge about the circuit’s current state b = 1 f = 0

  8. Logic Implications • Provide valuable diagnostic resolution • The checker hardware requires very little knowledge about the circuit’s current state sa0 sa0 sa1 sa0 sa0 b = 1 f = 0

  9. Hardware Implementation

  10. High Level Overview

  11. Test Set Selection Process

  12. Generating Pattern Scores • Scores reflect how valuable a pattern is for a given implication • While multiple detections of a fault are useful, we also wish to promote patterns that allow for full coverage of the faults detectable by an implication

  13. Step #1: Fault Dictionary and Implication Table

  14. Step #2: Select the Implication

  15. Step #2: Select the Implication

  16. Step #3: Calculate Scores

  17. Step #4: Pick the Pattern with the Highest Score

  18. Step #3 (again): Calculate Scores

  19. Step #3 (again): Calculate Scores

  20. Implication Assignment Table

  21. Experimental Setup

  22. Experimental Results

  23. Stuck-At Fault Detections

  24. Transition Fault Detections

  25. Experimental Results

  26. Conclusion • We have formulated a procedure for extracting diagnostic information from logic implications • This information was then used to target a specific area of the circuit that is suspected of having an error • Narrowing down the possible locations of an error allowed for the creation of very small, highly specialized test sets

  27. Future Work • Additional work could be done to narrow down the suspected sites even further • A given pattern will only detect a subset of the faults covered by an implication • The results of running patterns could further pinpoint a fault’s location

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