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ECE232: Hardware Organization and Design

ECE232: Hardware Organization and Design. Part 9: MIPS Lite 4 th edition: Chapter 4; 3 rd edition: Chapter 5 http://www.ecs.umass.edu/ece/ece232/. MIPS-lite processor. Computer. Want to build a processor for a subset of MIPS instruction set (“MIPS-lite”)

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ECE232: Hardware Organization and Design

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  1. ECE232: Hardware Organization and Design Part 9: MIPS Lite 4th edition: Chapter 4; 3rd edition: Chapter 5 http://www.ecs.umass.edu/ece/ece232/

  2. MIPS-lite processor Computer • Want to build a processor for a subset of MIPS instruction set (“MIPS-lite”) • just enough to illustrate key ideas • instruction set subset (3 groups): • arithmetic-logical: add, sub, and, or, slt • memory reference: lw, sw • control flow: j, beq • can we write real programs with just these? • Need up to 5 steps to execute any instruction in our subset Processor (CPU) IMemory MIPS Instructions Control Datapath DMemory

  3. 1. Read IM[PC] 2. Instruction Decode, PC = PC + 4, Register read 3. ALU operation, Branch address computation 4. LW/STORE in Data memory 5. Register Write Instruction Execution Steps Instruction Fetch Decode, Inc PC and Read Registers ALU Operation, Branch address Data Memory operation Write Back

  4. PC Step 1 Building a Datapath for MIPS (step 1) Step 1: instruction fetch Instruction Memory . . . PC-4PCPC+4PC+8 . .    add $t0,$t0,$t0 add $t0,$s1,$t0 lw $t1,20($s0) sw $t1,4($t0)   Flow of execution

  5. Datapath Step 1: Any Instruction A d d “4” 32-bit adder or ALU wired only for add PC Address Instruction Instruction Memory (IMem) Once program is loaded, IMem is read-only Clock

  6. Registers PC Step 2: Decode and Read Registers Building a Datapath for MIPS (step 2) Instruction Memory Step 1 R add $t0,$s1,$t0 0 17 8 8 0 32 op rs rt rd shamt funct

  7. Datapath Step 2: Any Instruction R add $t0,$t1,$t2 op rs rt rd shamt funct ReadRegister 1 Readdata 1 ReadRegister 2 Instruction Readdata 2 WriteRegister RegisterFile WriteData 6 Control Datapath Control Points

  8. Remaining Steps in Executing Instructions • 3rd step onwards depends on instruction class • EX: for ALU instructions: add $t0, $t1, $t2 outputs from registers t1 and t2 will be sent to the ALU input • For Memory-reference instruction: lw $t0,20($s0) Address  Base + offset A L U

  9. PC Registers Step 1 Step 2 Step 3 Building a Datapath for MIPS (lw step 3) A L U Instruction Memory lw $t0, 20($s0) I op rs rt address

  10. Datapath Step 3-4: R-format Instructions ALU control add, sub, and, or 3 ReadRegister 1 Readdata 1 [$t1] A L U Instruction Zero ReadRegister 2 Result WriteRegister Readdata 2 [$t2] [$t3] [$t1]  [$t2] WriteData Registers RegWrite [$t1]  [$t2] 32 { +, -, AND, OR, etc.}

  11. Datapath Step 3: Branch beq $t0,$t1,loop PC + 4from step 1 datapath A d d ALU control ReadRegister 1 3 Branchtarget Readdata 1 [$t0] Instruc- tion A L U ReadRegister 2 Result [$t1] Zero WriteRegister Readdata 2 To branch controllogic Mult by 4 WriteData Registers RegWrite SignExtend 32 16

  12. PC Registers Instruction Memory A L U Data Memory Step 2 Step 3 Step 1 Step 4 Steps 4,5 in Executing lw,sw lw $t1,20($s0) sw $t1,4($t0) • 4th step depends on instruction class • Ex: for lw: Fetch Data from Memory Data  Mem[Address] • For sw: Put the contents of a register in Memory From Register for SW To register for LW • 5th step only for lw; rest are done • for lw: Write Result Reg[rt]  Data

  13. Datapath Step 3-5: Load/Store lw $t0,24($s3) ALU control op rs rt address MemWrite ReadRegister 1 Readdata 1 [$s3] Zero Instruc- tion A L U ReadRegister 2 Readdata [$s3]+24 Address “24” Result WriteRegister Readdata 2 DMem WriteData Registers WriteData RegWrite SignExtend MemRead 16 32

  14. Compose Datapath: R-form + Load/Store Add muxes ALU control MemWrite 3 ReadRegister 1 Readdata Readdata 1 Zero A L U ReadRegister 2 Instruction MemTo- Reg0=R-form1=L/S Address Readdata 2 WriteRegister M u x DMem Registers WriteData WriteData 1 M u x 0 RegWrite ALUSrc 0 = R-format1 = Load/Store MemRead SignExtend 32 16

  15. Compose Datapath: + IMem + PC a d d “4” ALU control MemWrite ReadReg1 4 Read Addr Readdata P C Readdata1 Zero A L U ReadReg2 Instruc- tion Address Readdata2 MemTo- Reg WriteReg M u x IMem DMem Registers WriteData WriteData M u x ALUSrc RegWrite MemRead SignExtend 32 16

  16. a d d SignExtend Compose Datapath: + Branch “Left Shift 2” module M u x a d d << 2 “4” PCSrc MemWrite ReadReg1 Read Addr ALUcon P C Readdata Readdata1 Zero ReadReg2 A L U Instruc- tion Address Readdata2 MemTo- Reg WriteReg M u x IMem DMem Registers WriteData WriteData M u x Supports allMIPS-lite instructions? (slt and ?) ALUSrc RegWrite MemRead 32 16

  17. 6 bits 6 bits 5 bits 5 bits 5 bits 5 bits op rs rt rd shamt funct 6 bits 5 bits 5 bits 16 bits op rs rt offset Datapath: Register fields • Destination registers may differ across instruction formats: • R-format: [rd] [rs] op [rt]add $t0,$s0,$s1 For this instruction, bits 11-15 are the destination (t0), which should be connected to the write reg. inputs • I-format: [rt] mem[[rs] + imm16]lw $t0,24($s3) For this instruction, bits 16-20 should go to the write reg. port. Bits 0-15 go to the ALU as address • Connection to the write reg. port changes! • Solution? mux to the rescue!

  18. a d d SignExtend Datapath (add RegDst Mux) M u x a d d 4 << 2 PCSrc MemWrite 25:21 ReadReg1 Read Addr P C Readdata Readdata1 Zero ReadReg2 20:16 31:0 A L U Instruc- tion Address M u x Readdata2 MemTo- Reg WriteReg M u x DMem IMem Regs ALU- con WriteData WriteData 15:11 M u x RegDst ALU- src RegWrite MemRead 15:0

  19. Datapath: Determine next PC • What if instruction is a conditional branch (beq)? • if operands equal, take branch (PC gets PC+4+offset) • else PC gets PC+4 • Therefore, set control point PCSrc = 1 if and only if beq and Zero asserted

  20. a d d SignExtend Datapath (add Branch control point) M u x a d d << 2 4 PCSrc MemWrite 25:21 ReadReg1 Branch Read Addr P C Readdata Readdata1 Zero ReadReg2 31:0 20:16 A L U Instruc- tion Address Readdata2 M u x MemTo- Reg WriteReg M u x DMem IMem Regs ALU- con WriteData WriteData 15:11 M u x RegDst ALU- src RegWrite MemRead 15:0

  21. Adding Control • CPU = Datapath +Control • Single-Cycle Design: • Instruction takes exactly one clock cycle • Datapath units used only once per cycle • Writable state updated at end of cycle • What must be “controlled”? • Multiplexors (Muxes) • Writable components: Register File, Data Memory (DMem) • what about PC? IMem? • ALU (which operation?)

  22. Processor = Datapath + Control • Single-Cycle Design: everything happens in one clock cycle until next falling edge of clock, processor is just one big combinational circuit!!! • Control is a combinational circuit where the output is a function of the inputs • outputs? control points in datapath • inputs? the current instruction! (opcode, funct control everything) op rs rt rd shamt funct R-format instruction 6 6 Control Logic To datapath

  23. ALUcontrol Defining Control • Note that funct field only present in R-format instruction - funct controls ALU only • To simplify control, define Main control, ALU control separately – using multiple levels will also increase speed – important optimization technique • ALUop inputs will be defined MainControl op opfunct ControlLogic ALU- con ALUop funct

  24. Defining ALU Control ALUcon A B Zero Result A L U ALUcon ALU function Instruction(s) supported 0000 AND R-format (and) 0001 OR R-format (or) 0010 add R-format (add), lw, sw 0110 subtract R-format (sub), beq 0111 set on less than R-format (slt) 1100 NOR R-format (nor)

  25. Defining ALU Control Instruction Desired opcode ALU Action ALUOp funct ALUcon lw add 00 xxxxxx 0010 sw add 00 xxxxxx 0010 beq subtract 01 xxxxxx 0110 R-type add 10 100000 (add) 0010 R-type subtract 10 100010 (sub) 0110 R-type logical AND 10 100100 (and) 0000 R-type logical OR 10 100101 (or) 0001 R-type set on less 10 101010 (slt) 0111 ALUOp Funct Field a1 a0 f5 f4 f3 f2 f1 f0 ALUcon 0 0 x x x x x x 0010 x 1 x x x x x x 0110 1 x x x 0 0 0 0 0010 1 x x x 0 0 1 0 0110 1 x x x 0 1 0 0 0000 1 x x x 0 1 0 1 0001 1 x x x 1 0 1 0 0111 c3 c2 c1 c0 Don’t Cares

  26. OpCode field

  27. Function field

  28. Fully Minimized ALU Control a1,0 f5,4,3,2,1,0 ALUcon 0 0 x x x x x x 0010 X 1 x x x x x x 0110 1 x x x 0 0 0 0 0010 1 x x x 0 0 1 0 0110 1 x x x 0 1 0 0 0000 1 x x x 0 1 0 1 0001 1 x x x 1 0 1 0 0111 • From the truth table, output signals can be easily derived because of don’t cares • c2 = a0 OR (a1 AND f1) • c1 = (Not a1) OR (Not f2) • c0 (lsb) = a1 AND (f3 OR f0) A L U O p • ALUOp is supplied by the main control unit (to be designed) a0 a1 c2 F 3 ALUcon 4th bit=0 c1 F 2 funct F 1 c0 F 0

  29. a d d SignExtend Datapath + ALU Control M u x a d d << 2 “4” PCSrc MemWrite ReadReg1 Read Addr P C Readdata Readdata1 Zero ReadReg2 A L U Instruc- tion Address Readdata2 MemTo- Reg WriteReg M u x IMem DMem Registers ALU- con WriteData WriteData M u x ALU- src ALU Control RegWrite MemRead Instr[5:0] ALUOp

  30. Datapath With Control

  31. 2 address 31:26 25:0 Adding Jumps • Update PC with concatenation of • Top 4 bits of old PC • 26-bit jump address • 00 • Need an extra control signal decoded from opcode Jump

  32. Datapath With Jumps Added

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