CMOS RFIC Design for Direct Conversion Receivers

1. CMOS RFIC Design for Direct Conversion Receivers Zhaofeng ZHANG ELEC, HKUST

2. Outline of Presentation • Background Introduction • Design Issues and Solutions • A Direct Conversion Pager Receiver • Conclusion

3. Research Goal • Low Cost • Process: CMOS • Device is good enough • Improved passive components • Integration level • Minimize external components • Minimize IC area and pin numbers • Low Power • High integration = low power • Low power individual block design • System architecture is important SOC

4. Heterodyne Receivers • High IF: more than 2 down-conversions • Best sensitivity • Need off-chip image-rejection SAW filters and channel-selection filters • Highest cost, high power, low integration • Low IF • Relaxed image-rejection requirement compared to high-IF • No DC offset problem • Quadrature LO is required • Flicker noise may be a problem • High integration level, low cost

5. I 90º LNA Q Homodyne Receivers Pros Cons • Simple architecture • No image problem • No 50ohm interfaces • High integration level • Lowest cost, low power • DC offsets • Flicker noise • LO leakage • Even-order distortion

6. Origin of Problem • DC offsets • Flicker noise • LO leakage • Even-order distortion • Linearity requirement • Noise requirement • IQ mismatch All problems are limited by the mixer design! The mixer: the most critical component! Our research focus!

7. LO Leakage + Offset Zero IF DC Offsets & LO Leakage • The offset originates from self-mixing. • It can be as large as mV range at the mixer output. • It varies with the environment and moving speed of • the mobile and changes with time. • The maximum bandwidth can be as large as kHz range. • LO leakage forms an interference to other receivers.

8. Narrow Band Broad Band DC offset High-pass corner Power Power DC Offsets Frequency Frequency Flicker noise Signal Power Power Offset-Free Frequency Frequency Spectrum Illustration

9. Existing Solutions on DC Offset • AC coupling or high pass filtering • Autozeroing or double sampling • Offset cancellation in digital domain • Double LO frequency method [ISSCC99] • Adaptive dual-loop algorithm combined with the mixer [RAWCON00] • Pulse-width-modulation based bipolar harmonic mixer [CICC97] However, these methods are either not so effective or too complicated, or not suitable for CMOS process.

10. RF Signal BB Signal LO Leakage DC Offset Conventional frf 0 flo=frf 2flo=frf RF Signal BB Signal LO Leakage Our Work flo=frf/2 frf 0 flo Proposed Harmonic Mixing

11. 3V Voltage RF IF No Current Coupling Vrf- Vrf+ 2 Voltage LO Vlo- Vlo+ Square-law Based Mixer • LO leakage free. • Ideally self-mixing free. • Current controlled switching. • No noise contribution from LO stage.

12. 3V I0 Vrf- Vlo- Vlo+ Flicker Noise Reduction Vrf+ • Flicker noise is proportional to the current. • Current injection is used to reduce flicker noise. • No noise contribution from current source too.

13. Offset Cancellation 20 TSMC0.35 10 >35dB 0 -10 Gain (dB) -20 -30 -40 -22 -20 -18 -16 LO Input Power (dBm)

14. Noise Performance 60 50 40 Noise Figure @ 10kHz (dB) 30 20 400 600 800 1000 Injected Current I0 (A)

15. How to improve more? • However, flicker noise is still too large due to CMOS devices, minimum noise figure achieved is larger than 24dB @ 10kHz for CMOS harmonic mixer. It requires a high gain and low noise LNA to overcome flicker noise while the front-end linearity suffers. • For a narrow-band communication system such as FLEX pager, the noise requirement at low frequency is very tough. • It is well known that bipolar device is a good candidate to eliminate flicker noise. • But, can we do it in a CMOS process and how good is the device? YES!

16. W.T. Holman95 Emitter Base Gate Gate Emitter Vertical P+ N+ Collector Base Collector Lateral Collector Ground Lateral Bipolar Transistor in a Bulk CMOS Process

17. Gate D. Mac98 Collector Emitter M1 Q1 Base Base Q3 Q2 P-Sub P-Sub Pure LBJT: M1, Q3 off, Q1, Q2 on. Physical Model of LBJT

18. Gummel Plot of LBJT TSMC0.35 >40 at mAs max fT 4GHz

19. VDD VLO- VLO+ M1 M2 Ii Q1 Q2 VRF- VRF+ OUT- OUT+ RL RL LBJT Harmonic Mixer

20. Noise Performance Large LO improves noise.

21. RF Signal BB Signal Interference IM2 (f2-f1) frf 0 Even Order Distortion a1x+a2x2+a3x3+… f1 f2 • It is mainly introduced by layout asymmetry and device mismatch. • Since direct-conversion, the intermodulation components IM2 will fall into the demodulated signal spectrum. • Therefore, good IIP2 is required for homodyne receivers. • It is found that varying the loading resister or voltage bias can compensate the device mismatch and improve IIP2 significantly.

22. IIP2 Improvement Same DC bias Compensation IIP2=18dBm IIP2>40dBm

23. LBJT Mixer Performance

24. Summary on Mixer • Flicker noise free, corner frequency is below 10kHz. • DC offset free, more than 30dB DC offset suppression is achieved. • No LO leakage problem. • Sufficient IIP2 after bias compensation. • High gain and low power consumption. • Complete CMOS process. • Suitable for CMOS direct conversion applications.

25. FLEX 6400, 4FSK 0 -20 dB -40 -60 -10 -5 0 5 10 kHz 0 -1 -2 10 10 10 Difficulties in FLEX Pager -1 High pass effect BER @ 12dB Eb/N0 -2 10 High pass corner (Hz) Big Challenges • Narrow band modulation • Significant energy near DC • High pass filtering is not viable • DC offset problem • Flicker noise is significant DC Offset Effect BER 4 8 12 16 Eb/N0 (dB)

26. AGC AGC DEMOD LNA VCO 45 4-FSK Pager Receiver RF: Zhaofeng BB: Zhiheng • Fully differential architecture to reject substrate noise. • Harmonic mixers are used to solve time-varying DC offset. • Peak detectors are used to cancel static DC offset. • High front-end gain and current injection to reduce flicker noise.

27. LNA • Non-quasi-static phenomenon makes it unnecessary to do on-chip matching. • Off-chip matching by a single inductor and a balun. • |S11|<-20dB @ 930MHz • Both on-chip and off-chip inductive loads were tried.

28. Double Balanced Mixer Improve the linearity; Provide constant impedance to LNA; Current injection provides more than 20dB flicker noise reduction.

29. Ring Oscillator Half RF frequency, Provide 45 phase.

30. Zero-IF 4-FSK Signal Static DC Offset Cancellation Peak Detector Fmin200Hz

31. Front-EndOff-chip ind On-chip ind RF/BB gain: 51.13dB 40.33dB NF@10kHz: 11.5dB 24.0dB NF@100kHz: 5.8dB 15.0dB IIP3: -26dBm -20.7dBm IIP2: -10dBm -5.6dBm Operating frequency: 930.1MHz LO frequency: 465MHz IQ gain mismatch: < 0.3dB IQ phase mismatch: < 5 RF/BB over LO/BB: > 54dB Self-mixing free Input matching: < -20dB Power dissipation: 52.76mW Pager receiver with off-chip ind Maximum Gain: 62dB Noise figure@10kHz: 14.5dB Overall DC offset at LPF output: <1mV (Signal: 400mV) Power dissipation: 58mW Technology: TSMC0.35mm 4M2P Die area: 4.6 mm2 Baseband (Zhiheng) AGC gain: -14.5dB~18.6dB LPF: Pass-band gain-6.2dB, ripple 0.5dB (9kHz) Stop-band attenuation  63dB ( 17.8kHz) Offset cancellation: <2mV (under ±100mV input offset) Input Referred Noise: 600nV/ @ 10kHz Clock Recovery: Capture range > 550Hz Power dissipation: 5.4mW (including all testing buffers) Performance Summary

32. RF Front-End LNA DEMOD LPF OSC OSC LNA AGC Mixer Mixer AGC Base Band Circuitry[Zhiheng] RF Front-End LNA DEMOD VCO 45 AGC Die Photo

33. Summary on Pager Receiver • Feasibility of direct conversion has been demonstrated. • Proposed harmonic mixing technique solves self-mixing induced DC offset problem successfully. • With the help of static DC offset cancellation, the total DC offset is less than 1mV at the receiver output. • The modified ZIFZCD 4-FSK demodulator functions correctly. • A 4-FSK FLEX pager receiver in a single chip has been implemented successfully.

34. Conclusion • Circuit design for direct-conversion has been discussed. • DC offset: more than 30dB improvement • LO leakage: no longer a problem • Flicker noise: corner frequency is less than kHz due to lateral bipolar device. • IIP2: larger than +40dBm after bias compensation. • System on chip has been successfully demonstrated using CMOS direct conversion architecture.