IKI10230 Pengantar Organisasi Komputer Bab 14: Input/Output & Interrupt

1. IKI10230Pengantar Organisasi KomputerBab 14: Input/Output & Interrupt Sumber:1. Paul Carter, PC Assembly Language2. Hamacher. Computer Organization, ed-53. Materi kuliah CS61C/2000 & CS152/1997, UCB 19 Mei 2004 L. Yohanes Stefanus (yohanes@cs.ui.ac.id)Bobby Nazief (nazief@cs.ui.ac.id) bahan kuliah: http://www.cs.ui.ac.id/kuliah/POK/

2. Keyboard, Mouse Computer Processor (active) Memory (passive) (where programs, data live when running) Devices Disk(where programs, data live when not running) Input Control (“brain”) Datapath (“brawn”) Output Display, Printer Input/Output: Gerbang Ke Dunia Luar

3. Motivation for Input/Output • I/O is how humans interact with computers • I/O lets computers do amazing things: • Read pressure of synthetic hand and control synthetic arm and hand of fireman • Control propellers, fins, communicate in BOB (Breathable Observable Bubble) • Read bar codes of items in refrigerator • Computer without I/O like a car without wheels; great technology, but won’t get you anywhere

4. I/O Device Examples and Speed • I/O Speed: bytes transferred per second(from mouse to display: million-to-1) • Device Behavior Partner Data Rate (Kbytes/sec) Keyboard Input Human 0.01 Mouse Input Human 0.02 Line Printer Output Human 1.00 Floppy disk Storage Machine 50.00 Laser Printer Output Human 100.00 Magnetic Disk Storage Machine 10,000.00 Network-LAN I or O Machine 10,000.00 Graphics Display Output Human 30,000.00

5. Operating System Proc Mem PCI Bus SCSI Bus cmd reg. data reg. What do we need to make I/O work? Files Windows • A way to connect many types of devices to the Proc-Mem • A way to control these devices, respond to them, and transfer data • A way to present them to user programs so they are useful

6. Prosesor Bus DATAOUT DATAIN SOUT SIN Display Keyboard Organisasi Input/Output • I/O Device biasanya memiliki 2 register: • 1 register menyatakan kesiapan untuk menerima/mengirim data(I/O ready), sering disebut Status/Control Register SIN, SOUT • 1 register berisi data, sering disebut Data Register DATAIN, DATAOUT • Prosesor membaca isi Status Register terus-menerus, menunggu I/O device men-set Bit Ready di Status Register (0  1) • Prosesor kemudian menulis atau membaca data ke/dari Data Register • tulis/baca ini akan me-reset Bit Ready (1  0) di Status Register

7. Memory-mapped-I/O & I/O-mapped-I/O • Status & Data Registers are treated as memory locations: • Called “Memory Mapped Input/Output” • A portion of the address space dedicated to communication paths to Input or Output devices (no memory there) • The registers are accessed by Load/Store instructions, just like memory • Some machines have special input and output instructions that read-from and write-to Device Address Space: • Called “I/O Mapped Input/Output” • IN Rx,Device-Address ; Processor  Device ; Rx  Rdevice-Address • OUT Device-Address,Rx ; Device  Processor ; Rdevice-Address  Rx

8. Contoh Program Input/Output (Memory-mapped-I/O) • Input: Read from keyboard READ: MOV AL,[INSTATUS] ; Get kbd status AND AL,1 ; Is it ready? JZ READ ; Wait for key-inMOV AL,[DATAIN] ; Read character MOV [INBUF],AL ; Store it • Output: Write to displayECHO: MOV AL,[OUTSTATUS]; Get dsp status AND AL,10B ; Is it ready? JZ ECHO ; Wait until ready MOV AL,[OUTBUF] ; Load characterMOV [DATAOUT],AL ; Display it

9. Contoh Program Input/Output (I/O-mapped-I/O) • Input: Read from keyboard READ: IN AL,P_INSTAT ; Get kbd status AND AL,1 ; Is it ready? JZ READ ; Wait for key-inIN AL,P_DATAIN ; Read character MOV [INBUF],AL ; Store it • Output: Write to displayECHO: IN AL,P_OUTSTAT ; Get dsp status AND AL,10B ; Is it ready? JZ ECHO ; Wait until ready MOV AL,[OUTBUF] ; Load characterOUT P_DATAOUT,AL ; Display it

10. Polling

11. Processor-I/O Speed Mismatch • 500 MHz microprocessor can execute 500 million load or store instructions per second, or 2,000,000 KB/s data rate • I/O devices from 0.01 KB/s to 30,000 KB/s • Input: device may not be ready to send data as fast as the processor loads it • Also, might be waiting for human to act • Output: device may not be ready to accept data as fast as processor stores it • What to do?

12. Program-Controlled I/O: Polling • Input: Read from keyboard READ: IN AL,P_INSTAT ; Get kbd status OR AL,1 ; Is it ready? JZ READ ; Wait for key-inIN AL,P_DATAIN ; Read character MOV [INBUF],AL ; Store it • Output: Write to displayECHO: IN AL,P_OUTSTAT ; Get dsp status OR AL,10B ; Is it ready? JZ ECHO ; Wait until ready MOV AL,[OUTBUF] ; Load characterOUT P_DATAOUT,AL ; Display it • Processor waiting for I/O called “Polling” DATAIN STATUS DATAOUT

13. Cost of Polling? • Assume for a processor with a 500-MHz clock it takes 400 clock cycles for a polling operation (call polling routine, accessing the device, and returning). Determine % of processor time for polling • Mouse: polled 30 times/sec so as not to miss user movement • Floppy disk: transfers data in 2-byte units and has a data rate of 50 KB/second. No data transfer can be missed. • Hard disk: transfers data in 16-byte chunks and can transfer at 8 MB/second. Again, no transfer can be missed.

14. % Processor time to poll mouse, floppy • Times Mouse Polling/sec = 30 polls/sec • Mouse Polling Clocks/sec = 30 * 400 = 12000 clocks/sec • % Processor for polling: 12*103/500*106 = 0.002%  Polling mouse little impact on processor • Times Polling Floppy/sec = 50 KB/s /2B = 25K polls/sec • Floppy Polling Clocks/sec = 25K * 400 = 10,000,000 clocks/sec • % Processor for polling: 10*106/500*106 = 2%  OK if not too many I/O devices

15. % Processor time to hard disk • Times Polling Disk/sec = 8 MB/s /16B = 500K polls/sec • Disk Polling Clocks/sec = 500K * 400 = 200,000,000 clocks/sec • % Processor for polling: 200*106/500*106 = 40%  Unacceptable

16. Interrupt

17. What is the alternative to polling? • Wasteful to have processor spend most of its time “spin-waiting” for I/O to be ready • Wish we could have an unplanned procedure call that would be invoked only when I/O device is ready • Solution: use interrupt mechanism to help I/O. Interrupt program when I/O ready, return when done with data transfer

18. I/O Interrupt • An I/O interrupt is like a subroutine call except: • An I/O interrupt is “asynchronous” • More information needs to be conveyed • An I/O interrupt is asynchronous with respect to instruction execution: • I/O interrupt is not associated with any instruction, but it can happen in the middle of any given instruction • I/O interrupt does not prevent any instruction from completion

19. (1) I/O interrupt Memory add sub and or (2) save PC user program (3) interrupt service addr (4) read mov ... iret interrupt service routine (5) Interrupt Driven Data Transfer

20. Benefit of Interrupt-Driven I/O • 400 clock cycle overhead for each transfer, including interrupt. Find the % of processor consumed if the hard disk is only active 5% of the time. • Interrupt rate = polling rate • Disk Interrupts/sec = 8 MB/s /16B = 500K interrupts/sec • Disk Transfer Clocks/sec = 500K * 400 = 200,000,000 clocks/sec • % Processor for during transfer: 250*106/500*106= 40% • Disk active 5%  5% * 40%  2% busy Determined by disk’s activity, whereas in Polling-driven I/O the Processor will be busy polling 40% of the time even if the disk is not active

21. Instruction Set Support for I/O Interrupt • Save the PC for return • To enable the “proper return” when the interrupt has been served • Intel x86 provides IRET – return from interrupt handler • Where to go when interrupt occurs? • To allow “proper branch” to the service routine • Intel x86 provides IDT (Interrupt Descriptor Table) that contains service routine addresses • Determine cause of interrupt? • To guarantee “proper service routine” serving “proper interrupt” • Intel x86 provides interrupt vector as a way to identify an interrupt

22. Exceptions

23. Exceptions • Interrupt is only a subset of Exception • Exception: signal marking that something “out of the ordinary” has happened and needs to be handled • Interrupt: asynchronous exception • Unrelated with instruction being executed • Trap: synchronous exception • Related with instruction being executed • To recover from errors: Illegal Instruction, Divide By Zero, … • To debug a program • To provide privilege (for Operating System)

24. DMA

25. Improving Data Transfer Performance • What about data transfer to I/O device? • Processor busy doing loads/stores between memory and I/O Data Register: Wait:in al,DiskControlcmp al,1 ; is Disk ready?jne Wait ; noin al,DiskData ; get bytemov [edi],al ; store itinc edidec ecx ; done?jnz Wait; not yet • Ideal: specify the block of memory to be transferred, be notified on completion? • Direct Memory Access (DMA) : a simple computer transfers a block of data to/from memory and I/O without involving the processor, interrupting upon done

26. Delegating I/O Responsibility from the CPU: DMA CPU sends a starting address, direction, and length count to DMAC. Then issues "start". • Direct Memory Access (DMA): • External to the CPU • Act as a maser on the bus • Transfer blocks of data to or from memory without CPU intervention CPU Memory DMAC IOC Issue: • Who controls the BUS?(CPU or DMAC may do so) • How? device DMAC provides handshake signals for Peripheral Controller, and Memory Addresses and handshake signals for Memory.

27. BUS

28. A Computer System with One Bus: Backplane Bus Backplane Bus • A single bus (the backplane bus) is used for: • Processor to memory communication • Communication between I/O devices and memory • Advantages: Simple and low cost • Disadvantages: slow and the bus can become a major bottleneck • Example: IBM PC - AT Processor Memory I/O Devices

29. A Two-Bus System Processor Memory Bus • I/O buses tap into the processor-memory bus via bus adaptors: • Processor-memory bus: mainly for processor-memory traffic • I/O buses: provide expansion slots for I/O devices • Apple Macintosh-II • NuBus: Processor, memory, and a few selected I/O devices • SCCI Bus: the rest of the I/O devices Processor Memory Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus I/O Bus I/O Bus

30. Bus Adaptor Bus Adaptor A Three-Bus System Processor Memory Bus • A small number of backplane buses tap into the processor-memory bus • Processor-memory bus is used for processor memory traffic • I/O buses are connected to the backplane bus • Advantage: loading on the processor bus is greatly reduced Processor Memory Bus Adaptor I/O Bus (e.g.,SCSI) Backplane Bus (e.g.,PCI) I/O Bus

31. What defines a bus? Transaction Protocol Timing and Signaling Specification Bunch of Wires Electrical Specification Physical / Mechanical Characterisics – the connectors

32. Summary of Bus Options • Option High performance Low cost • Bus width Separate address Multiplex address & data lines & data lines • Data width Wider is faster Narrower is cheaper (e.g., 32 bits) (e.g., 8 bits) • Transfer size Multiple words has Single-word transfer less bus overhead is simpler • Bus masters Multiple Single master (requires arbitration) (no arbitration) • Clocking Synchronous Asynchronous • Protocol pipelined Serial