DDRIII BASED General Purpose FIFO on Virtex-6 FPGA ML605 board PART B presentation

1. DDRIII BASED General Purpose FIFO on Virtex-6 FPGA ML605 boardPART B presentation Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf Semester: spring 2013

2. Content • Project overview • Specifications • Part B goals • Memory on ml605 • AXI4 • Part A overview • Part B overview • Design • Performance

3. Project Overview • Design and implementation of General Purpose FIFO IP core which allows usage of external memory (DDR3) as FIFO storage on Xilinx FPGA device • Design and implement generic IP core of FIFO • Design and implement GUI generator of IP core on PC • Create sample design with implemented IP core

4. Specifications • Hardware • Xilinx Virtex-6 ML605 FPGA Evaluation Kit • DDR III memory • Ethernet interface • PC with Ethernet interface • Software • ISE Design Suite Logic Edition Version 14.3 • Modelsim • Wireshark • Winpcap library

5. MEMORY on ml605 • DDR3 memory • Capacity: 512MB • Max theoretical bandwidth: 800MT/s*64bit = 48.8Gb/sec • Xilinx provides us with DDR3 controller which has AXI Memory Mapped interface • AXI bus data width up to 1024 bit • 256 bit for max memory performance, assuming bus works with 200Mhz

6. 4AXI • Xilinx provides us with AXI4 Memory Mapped bus, which is a standard bus used in modern ARM SoC. • Features • Separate Address/Control and Data Phases • burst-based transactions with only start address issued • separate read and write data channels

7. General purpose Fifo AXI4 Interface CONTROLLER FIFO TO MEMORY MEMORY TO FIFO FIFO FIFO Native Fifo Interface

8. General purpose Fifo interface AXI4 Native FIFO GP FIFO

9. part Aoverview general purpose Fifo • Interface • GP FIFO has native FIFO interface • In Word size is 32 bit • Out Word size is 32 bit • Utilizes DDR3 memory through AXI interconnect 32 bit wide • Depth is limited only by available RAM memory on DDR3 • Same clock domain for IN and OUT • Internal architecture • Internal FIFO-To-Memory controller • Internal Memory-To-FIFO controller • Internal Bypass controller • Arbitration between GP FIFOs is managed by AXI interconnect

10. Example DESIGN Block Diagram DDR3 HOST STORAGE USER STORAGE LOGIC STORAGE MEMORY CONTROLLER AXI4 BUS (INTERCONNECT) General Purpose Fifo General Purpose Fifo MAC Module MAC Controller HOST Example Design

11. part a overview example design • Interface • Utilizes Ethernet MAC level of communication • Software has simple and intuitive interface • Software handles all the data transmission in between host and GP FIFO • Internal architecture • MAC module • GP FIFO • Simple example of a logic which uses GP FIFO • Example design of part A is dedicated to verify GP FIFO core under maximum performance condition. In part B we tested different configurations (variable word size).

12. Our goals part b • Generalize our GP FIFO • Develop software generator for GP FIFO IP core • Write detailed manual for IP core and for it’s generator • Develop simple design to test performance • Simulate and test all the possible configurations and their exceptional case • Make possible optimizations

13. part B overview general purpose Fifo • Interface • GP FIFO has native FIFO interface • GP FIFO has configurable internal word size: 64, 128, 256 bit • In/Out word size can be 8, 16, 32, 64, 128, 256 bitMaximum ratio of internal word size to In/Out is x8 • Depth is defined by two addresses: start and end.Those two addresses define continuous region of memory which is used for GP FIFO and thus its depth. • Same clock domain for reader and writer • Internal architecture • Input and output buffers has fixed depth of 128 wordsto maximize performance

14. part B overview software generator for GP FIFO IP core • Developed in Java • Available GP FIFO core configuration parameters • Name • Start address of utilized RAM memory • End address of utilized RAM memory • In word size • Out word size • Internal word size: 64b, 128b, 256b • Maximum ratio of internal word size to In/Out is x8

15. part B overview software generator for GP FIFO IP core

16. part B overview software generator for GP FIFO IP core • Provides user with a convenient way of GP FIFO parameterization • Prepares simulation of generated GP FIFO

17. Example DESIGN Block Diagram DDR3 HOST STORAGE USER STORAGE LOGIC STORAGE MEMORY CONTROLLER AXI4 BUS (INTERCONNECT) General Purpose Fifo Example Design MAC Module MAC Controller HOST

18. part B overview example design • Example design of part B is dedicated to measure maximum performance of GP FIFO core with different configurations. • Interface with host • Utilizes Ethernet MAC level of communication • Software developed in Part A • Internal architecture • MAC module • GP FIFO • Simple logic • Simultaneously writes/reads GP FIFO. • Sends word count to Host every second.

19. part B overview performance of different configurations • We defined three stages in exploring performance of GP FIFO under different configurations. GP FIFO of size 64Mb In/Out is symmetric (variable) Example Design and GP FIFO are running with 200MHz clock • Performance dependence on depth of In/Out buffer • Internal word size 64 bit • In/Out buffer depth is variable • Performance dependence on internal word size • Internal word size: 128, 256 bit is variable • In/Out buffer depth is 128 words

20. part B overview performance dependence on in/out buffer depth

21. part B overview performance dependence on in/out buffer depth

22. part B overview performance dependence on in/out buffer depth

23. part B overview performance dependence on internal word size

24. part B overview performance dependence on internal word size

25. part B overview performance dependence on internal word size

26. part B overview performance dependence on internal word size

27. part B overview performance of different configurations • Performance dependence on depth of In/Out buffer • Deeper buffer results in higher average speed only when in/out word size is greater/equals internal word size • Performance dependence on internal word size • Increasing internal word size provides significant speedup • Optimal internal word size is twice as in/out word size • Experiment shows that speed of GP FIFO in real design correlates well with simulated values • Conclusion • Changing buffer depth can hide some latency in case of not optimal internal word size, does not provide significant speedup to the system • Optimal internal word size is x2 max{in, out} word size

28. Project overview • Our design meets the requirements of the project. • GP FIFO is fast limited only by interconnect bus available bandwidth • GP FIFO has configurable depth and word size • GP FIFO is simple, utilizes small amount of resources on the board • GP FIFO gives you another easy way to pass big chunks of data from one module to another. • GP FIFO core generator provides an easy way to configure the core. • Our example design provides you with efficient communication in between a host and the board. • After one and a half year of hard work we finally reached all sgoals of the project