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Ideal package power planes - PowerPoint PPT Presentation

Package-Chip Co-Design

Prof. Lei He Electrical Engineering Department, UCLA LHE@ee.ucla.edu http://eda.ee.ucla.edu. Package-Chip Co-Design. Outline. Overview of Chip Package Co-design IO planning and placement Power integrity in package Reading: package tutorial at ee201c wiki. Wire-bond vs Flip-chip.

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Chapter 6a IC/Package Co-Design for Power Integrity

Chapter 6a IC/Package Co-Design for Power Integrity. Prof. Lei He Electrical Engineering Department University of California, Los Angeles URL: eda.ee.ucla.edu Email: lhe@ee.ucla.edu. Outline. Overview of Chip Package Co-design IO planning and placement Design constraints

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Ideal package power planes - PowerPoint PPT Presentation

Package-Chip Co-Design

Chapter 6a IC/Package Co-Design for Power Integrity