'Low swing' diaporamas de présentation

Optimizing Power @ Design Time Memory

Optimizing Power @ Design Time Memory. Role of Memory in ICs. Memory is very important Focus in this chapter is embedded memory Percentage of area going to memory is increasing. [Ref: V. De, Intel 2006]. Processor Area Becoming Memory Dominated.

843 views • 37 slides

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0

Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. Naveen Muralimanohar Rajeev Balasubramonian Norman P Jouppi. 1. Large Caches. Intel Montecito. Cache hierarchies will dominate chip area

488 views • 30 slides

Guy Lemieux , Mehdi Alimadadi, Samad Sheikhaei, Shahriar Mirabbasi

277 views • 27 slides

A Charge Pump Based Receiver Circuit to Reduce Interconnect Power Dissipation

A Charge Pump Based Receiver Circuit to Reduce Interconnect Power Dissipation. Aatmesh Shrivastava, John Lach, and Benton H. Calhoun University of Virginia, Charlottesville. Interconnect Power Dissipation. [1] Magen , et. al. SLIP 2004.

352 views • 24 slides

A Charge Pump Based Receiver Circuit to Reduce Interconnect Power Dissipation

A Charge Pump Based Receiver Circuit to Reduce Interconnect Power Dissipation. Aatmesh Shrivastava, John Lach, and Benton H. Calhoun University of Virginia, Charlottesville. Interconnect Power Dissipation. [1] Magen , et. al. SLIP 2004.

248 views • 24 slides

Highly-Associative Caches for Low-Power Processors

Highly-Associative Caches for Low-Power Processors. Michael Zhang Krste Asanovic {rzhang|krste}@lcs.mit.edu. Motivation. Cache uses 30-60% processor energy in embedded systems. Example: 43% for StrongArm-1 Many academic studies on cache

263 views • 18 slides

Highly-Associative Caches for Low-Power Processors

Highly-Associative Caches for Low-Power Processors. Michael Zhang Krste Asanovic {rzhang|krste}@lcs.mit.edu. Motivation. Cache uses 30-60% processor energy in embedded systems. Example: 43% for StrongArm-1 Many academic studies on cache

257 views • 18 slides

Interconnect-Oriented Architecture and Circuits

Interconnect-Oriented Architecture and Circuits. William J. Dally Computer Systems Laboratory Stanford University February 12, 1998. On-chip wires. 0.0mm. 2.5mm. Minimum width wire in an 0.35 m m process. 5.0mm. 7.5mm. 10.0mm. On-chip wires are getting slower. x 2 = s x 1 0.5x

289 views • 18 slides