'Mini cache energy' diaporamas de présentation

Aviral Shrivastava* , Ilya Issenin, Nikil Dutt

M. C. L. A Compiler-in-the-Loop (CIL) Framework to Explore Horizontally Partitioned Cache (HPC) Architectures. Aviral Shrivastava* , Ilya Issenin, Nikil Dutt. ACES Lab, Center For Embedded Computer Systems, University of California, Irvine, CA, USA. *Compiler and Microarchitecture Lab,

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