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3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits

3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits

3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits. Rajesh Garg Sunil P. Khatri Department of ECE Texas A&M University College Station, TX. Outline. Background and Motivation Previous Work Simulation Setup Results and Discussions

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343 views • 26 slides
SEU Hardened Clock Regeneration Circuits

SEU Hardened Clock Regeneration Circuits

SEU Hardened Clock Regeneration Circuits. By: Rajballav Dash Rajesh Garg Sunil P. Khatri Gwan Choi Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX. Outline. Background Motivation Previous Work Our Approach Experimental Results

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479 views • 25 slides
A Novel, Highly SEU Tolerant Digital Circuit Design Approach

A Novel, Highly SEU Tolerant Digital Circuit Design Approach

A Novel, Highly SEU Tolerant Digital Circuit Design Approach. By: Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX. Outline. Background and Motivation Previous Work Our Approach Experimental Results Conclusions.

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322 views • 19 slides
A Novel, Highly SEU Tolerant Digital Circuit Design Approach

A Novel, Highly SEU Tolerant Digital Circuit Design Approach

A Novel, Highly SEU Tolerant Digital Circuit Design Approach. By: Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX. Outline. Background and Motivation Previous Work Our Approach Experimental Results Conclusions.

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200 views • 19 slides

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