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S hit rate limiter - PowerPoint PPT Presentation

MIPP TDC Card

MIPP TDC Card. Wu, Jinyuan Fermilab, PPD/EED Apr. 2007. The TDC Card. MIPP_TDC FPGA. 96 Channels. 12 connectors, 8ch each. Each MIPP_TDC FPGA digitize 48 channels inputs. The MIPP_DCC FPGA concentrate data from two TDC FPGA devices. Up to 32K event/spill are stored in the SDRAM.

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MIPP TDC Card