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Chapter 5: A Multi-Cycle CPU

Chapter 5: A Multi-Cycle CPU. The Multi-cycle idea. We can use any logic block once each cycle. PC. Read reg. 1. Read address. Read data 1. Memory. Read reg. 2. Read data. Registers. Result. Write address. Write reg. Read data 2. Write data. Write data. Memory:

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EE204 Computer Architecture

EE204 Computer Architecture. Processor Datapath. Homework 2 is out. Add. Read address. PC. Instruction. Instruction Memory. Instruction Datapath. 4. Instructions will be held in the instruction memory The instruction to fetch is at the location specified by the PC Instr. = M[PC].

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Memory

Sh. Left 2. 2. 0. 1. Registers. PC. 0. 0. Read reg num A. Read address. Read reg data A. 1. 1. Memory. Read reg num B. Zero. Read data. Instr. [31-0]. Result. Write address. 0. Write reg num. 0. Read reg data B. Instruction Register. 1. Write data. 1. Write reg data. 2.

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Write reg data - PowerPoint PPT Presentation

Chapter 5: A Multi-Cycle CPU

EE204 Computer Architecture

Memory