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SAR-ATR/FOA Compiler for ACS

SAR-ATR/FOA Compiler for ACS. SLAAC Retreat, March ‘99 Brad L. Hutchings Configurable Computing Lab Brigham Young University. Joint STARS ‘97 SAR ATR Pipeline. SAR Image. Annotated SAR Image. T72. T72. *Not Joint STARS imagery. Identification. PGA. Detection. Joint STARS

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SAR-ATR/FOA Compiler for ACS

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  1. SAR-ATR/FOA Compiler for ACS SLAAC Retreat, March ‘99 Brad L. Hutchings Configurable Computing Lab Brigham Young University

  2. Joint STARS ‘97 SAR ATR Pipeline SAR Image Annotated SAR Image T72 T72 *Not Joint STARS imagery Identification PGA Detection Joint STARS Advance Workstation (JAWS) ATR Results Display ESAR Image Focus of Attention Indexer (SLD) Belief Management (Fusion Executive) MPM MSE CRM LPM..

  3. AIQ Binary Morphology Joint STARS ‘97 SAR ATR Pipeline Sandia National Labs SAR Image Annotated SAR Image T72 T72 *Not Joint STARS imagery Identification PGA Detection Joint STARS Advance Workstation (JAWS) ATR Results Display ESAR Image Focus of Attention Indexer (SLD) Belief Management (Fusion Executive) MPM MSE CRM LPM..

  4. Wish List • No circuit design • Automated mapping. • Fast compile times. • 10x or better performance. What the ATR programmer wants... quant 1 2 3 span 0 2 4 1 span 2 4 2 3 cover 4 0 ... Go-Fast BoxTM ATR Guy

  5. What the ATR programmer gets…(current state of the art) • Must be circuit designer. • No automated mapping. • Slow compile times (days). • 10x or better performance. Yikes! Box of GatesTM ATR Guy

  6. quant 1 2 3 span 0 2 4 1 span 2 4 2 3 cover 4 0 ... span 0 2 4 1 span 2 4 2 3 cover 4 0 ... FOA .def file (binary morphology) We are getting close to the ideal.(.def files in, bitstreams out). BYU-FOA Compiler 8 minutes 5, XC4062 Xilinx Bitstreams ATR Guy 10X Faster ACS Platform

  7. 10x 50x 25x 8x 10x SLAAC SAR/ATR Roadmap - 500:1 Acceleration vs. ‘96 Baseline 1000 Hybrid ACS (e.g. RISC core, RTR) Heterogeneous ACS (e.g. memory on chip) • Arch. Advantage Goal • Fine-grain parallelism • Fine-grain control • Dynamic load balance • Precision management • Skip “0” • Early outs Performance 100 Homogeneous ACS FPGAs upgrade to latest technology. 10 ACS Initial Arch. Advantage Fine-grain parallelism Coarse-grain control Moore’s Law SLAAC 1 01 96 97 99 00 98 Baseline -- ‘96 PPC Year PowerPC BYU ACS FOA Performance (10x PowerPC) (morphology portion) SLAAC

  8. Superquant • Adaptive image quantization (AIQ). • Histogram generation and search. • First stage of the FOA algorithm. • Memory-bandwidth limited, not compute-bound. • Implementation • Exploits distributed memories. • Fully parameterizable (uses .def file). • Status: • Histogram processors have been designed and verified. • Projected pixel rates: • estimated, Xilinx 4K: 6-7 Mpixel (30 MHz). June 99. • estimated, Xilinx Virtex: 12-14 Mpixel (60 MHz). ?

  9. FOA Future Vision (Virtex) Image Data • 3 Chip Solution • 1 board • 30 Mpixel Superquant Superquant Binary Morphology Output

  10. Future Issues • Release source of BYU-FOA compiler to Sandia. • AIQ (adaptive image quantization) aka Superquant • Initial designs are complete. • CDI • Studying specification. • Study advantages of Xilinx Virtex. • Faster clocks, fewer chips, lower cost, yada, yada, yada...

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