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Team 1 Design Review – 2005/9/28

IEE 5644 Mixed-Signal IC Design and Laboratory (I). Team 1 Design Review – 2005/9/28. Outline. High-Speed PAM Transceivers Analog Circuit Elements for Digital Control High-Speed A/D Conversion High-Speed Clock/Phase Generation Conclusions. Transceiver Functions. Encoding and Decoding.

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Team 1 Design Review – 2005/9/28

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  1. IEE 5644 Mixed-Signal IC Design and Laboratory (I) Team 1 Design Review – 2005/9/28

  2. Outline • High-Speed PAM Transceivers • Analog Circuit Elements for Digital Control • High-Speed A/D Conversion • High-Speed Clock/Phase Generation • Conclusions Pipelined ADC

  3. Transceiver Functions • Encoding and Decoding. • Waveform Shaping. • Adaptive Equalization. • Feed-forward Equalization (FFE). • Decision-Feedback Equalization (DFE). • Adaptive Timing Recovery. • Analog-Digital Interfaces. • DAC and ADC. • Adaptive Gain and Offset Controls. Pipelined ADC

  4. PAM Transceiver Architecture The bit-error rate (BER) is determined by the signal-to-noise ratio (SNR) of Q(k). Pipelined ADC

  5. Eye Diagram Source: R. Walker, ISSCC short course, Feb. 2002. Pipelined ADC

  6. Conclusions • Technology and voltage scaling will continue. • More digital signal processing will be applied to future high-speed physical-layer data transceivers. • Technology scaling, especially the voltage scaling, isn’t good for analog circuits. Pipelined ADC

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