Nanotechnology: Spatial Computing Using Molecular Electronics

1. Nanotechnology: Spatial Computing Using Molecular Electronics Mihai Budiu joint work with Seth Copen Goldstein Dan Rosewater

2. Nanotechnology Computer architecture Intersection of Three Areas Reconfigurable computing

3. Prophecies, A Risky Endeavor There is no reason anyone would want a computer in their home. --- Ken Olson I think there is a world market for maybe five computers. --- T. J. Watson There is not the slightest indication that nuclear energy will ever be obtainable. --- Albert Einstein 640K ought to be enough for everybody. --- Bill Gates I will propose this semester. --- Anonymous

4. Moore’s Law

5. Moore’s Second Law X 1000$ generation Plant cost Mask cost

6. Our Proposal • Nanotechnology • cheap • high-density • low-power • unreliable • Reconfigurable • Computing • defect tolerant • high performance • low density _ + + + _ + + _ + _ • Computer architecture • vast body of knowledge • expensive • high-power

7. Paradigm Shift Configuration Executable Dense, regular structure + Configuration Complex fixed chip + Program

8. Outline • Introduction • Reconfigurable computing • Nanotechnology • Nano-architecture proposal • Preliminary results • Conclusions and Future Work

9. Reconfigurable Computing • Back to ENIAC-style computing • Synthesize one machine to solve one problem

10. Interconnection network Universal gates and/or storage elements Programmable Switches Island-Style RC Architecture

11. Main RC Ingredient: RAM Cell 0 0 0 1 a0 data a0 a1 & a2 a1 a1 Universal gate = RAM data in 0 control Switch controlled by a 1-bit RAM cell

12. Place and Route int reverse(int x) { int k,r=0; for (k=0; k<64; k++) r |= x&1; x = x >> 1; r = r << 1; } } int func(int* a,int *b) { int j,sum=0; for (j=0; *a>0; j++) sum+=reverse(*b

13. 1000 189.7 100 63.3 57.1 42.4 29.0 26.0 15.5 12.0 11.3 10 1 FIR ATR DCT Over IDEA Cordic DCT-2D Nqueens PopCount Kernel Speedup Using PipeRench Times Over 300Mhz UltraSparc-II

14. Defect Tolerance • Despite having >70% of the chips defective, Teramac works flawlessly. • Compilation has two phases: • defect detection through self-testing • placement for defect-avoidance

15. Outline • Introduction • Reconfigurable computing • Nanotechnology • Nano-architecture proposal • Preliminary results • Conclusions and Future work

16. Nanotechnology

17. Predicted Features • Low Power: 1010 gates use less than 2 W (compare to 3x107 transistors using 100 W in CMOS) • Low cost (nanocents/gate) • Small size (105 factor area gain) Nano-RAM cell . In yellow: a CMOS RAM cell

18. Nano-wires • carbon nanotubues, Si, metal • >2nm diameter, up to mm length • excellent electrical properties A carbon nanotube: one molecule

19. Nano-switch

20. Nano-switch Between Nano-wires

21. Self-assembly

22. No Complex Irregular Structures

23. No Three-Terminal Devices

24. V DD Output Input 1 Input 2 Diode-resistor Logic V V V V AND AND B B A A A B A * B A ^ B A * B Nano-implementation Electrical equivalent

25. Nanoscale Latches • Provide: • signal restoration (amplification) • clocking (synchronization) • memory data out D clock

26. High Defect Rate

27. Outline • Introduction • Reconfigurable computing • Nanotechnology • Nano-architecture proposal • Preliminary results • Conclusions and future work

28. The nanoBlock (3-in to 3-out Logic) CMOS Inputs +Vdd clk Gnd Gnd clk Outputs

29. Interconnecting nanoBlocks Switch block

30. Global View

31. Many Clusters = nanoFabric Control cluster long-lines

32. Compilation int reverse(int x){ int k,r=0; for (k=0; k<64; k++) r |= x&1; x = x >> 1; r = r << 1; }} • Program • Split-phase Abstract Machines • Configurations placed independently • Placement on chip Computations & local storage Unknown latency ops.

33. Outline • Introduction • Reconfigurable Hardware • Nanotechnology • Nano-architecture proposal • Preliminary results • Conclusions and Future work

34. Control-flow transfer Basic block Memory write Memory read Memory word A Limit Study of Performance A graph of the whole program execution:

35. Area(106 units/cm2 available)

36. Typical Program Graph (g721_e) Memory reads Control flow transfer 100% code cluster 100% memory cluster

37. Typical Program Graph (g721_e) Memory reads Control flow transfer code memcpy memory

38. Program Graph After Inlining memcpy memcpy

39. Application Slowdown

40. How Time Is Spent No caches: reads expensive No speculation

41. Future Work • Better nano-devices • More accurate hardware models in simulations • Compilation technology

42. Conclusions • Electronic nanotechnology promises to transcend the limitations of CMOS • Nanofabrics are very well suited to reconfigurable computation • 109-gate designs can be managed through hierarchies of abstract machines