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Design and CAD Challenges in sub-90nm CMOS Technologies

Design and CAD Challenges in sub-90nm CMOS Technologies. Kerry Bernstein Ching-Te Chuang Rajiv V. Joshi Ruchir Puri IBM T. J. Watson Research Center Yorktown Heights, NY 10598. Outline. Introduction CMOS device scaling New devices for high-performance logic

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Design and CAD Challenges in sub-90nm CMOS Technologies

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  1. Design and CAD Challenges in sub-90nm CMOS Technologies Kerry Bernstein Ching-Te Chuang Rajiv V. Joshi Ruchir Puri IBM T. J. Watson Research Center Yorktown Heights, NY 10598

  2. Outline • Introduction • CMOS device scaling • New devices for high-performance logic • Planar device structures (Chuang) • Partially-depleted (PD) SOI • Fully-depleted (FD) SOI • Strained-Si & high-k gate • Emerging technologies (Bernstein) • Double-gate MOSFETs • 3D integration and interconnects • Carbon Nanotube Transistor (CNT) • Molecular computing • CAD challenges (Puri) • Challenges of Advanced device technologies • Major issues • Power crisis • Coping with Variability

  3. Bulk CMOS Device Scaling Limit • Severe short channel effect (SCE) • Xdmax scaled with L to contain off-state leakage • High NB • Mobility degradation • Junction edge leakage due to tunneling • Dopant profile control (depth and steepness) difficult • tox scaled with L to maintain gate control, VT , & performance • High gate tunneling current • New device structures and materials • Short channel effect control by geometry • Off-state leakage limited by lightly-doped thin silicon film • High k gate dielectric to alleviate gate tunneling current • Mobility enhancement via strained Si surface channel devices • Desired VTand performance achieved by gate • workfunction engineering (e.g. Mid-gap, poly-SiGe)

  4. High-Performance Logic Technology (FD SOI: B. Doris et al., IEDM, 2002; FinFET: J. Kedzierski et al., IEDM 2001 Strained Si on SOI with raised S/D: B. H. Lee et al., IEDM, 2002)

  5. Planar Device Structures • Partially-depleted (PD) SOI • Parasitic bipolar and reduced-VT leakage • Hysteretic VT variation • Low-voltage impact ionization • VT,lin • Scaling/thinning of Si film (from PD SOI to FD SOI) • Major design issues • Gate oxide tunneling current • Self-heating • Soft Error Rate (SER) • Strained-Si and high-k gate • Summary

  6. PD SOI: Parasitic Bipolar Effect • “Off” Tx with S/D conditioned to “High”  High VBody • Source subsequently pulled down  Parasitic bipolar current & reduced-VT FET leakage  Dynamic node voltage droop

  7. Parasitic Bipolar Effect • Problem circuit topologies • Stacked OR-AND structures (e. g. wide dynamic OR) • Pass-transistor based ckts (e.g. high fan-in mux) • Multi-level voltage-switch current steering ckts (e.g. dynamic CVSL XOR) • SRAM bitline structure • Aggregate parasitic bipolar effect of unselected cells on the selected bitline causes Write/Read disturb and limits the number of cells that can be attached to a bitline pair • Typically more significant at first cycle after long time of dormancy • Dynamic Circuit Techniques (D. H. Allen et al., ISSCC, 1999) • Pre-discharging intermediate nodes or body • Re-ordering pulldown stack or cross-connecting fingered stacks, • Force parasitic bipolar current to occur during precharge phase, • Complex domino

  8. Scaled PD SOI: Parasitic Bipolar & Reduced VT Leakage • Parasitic bipolar effect less significant w.r.t. increased FET current drive + VDD scaling reduces overdrive across B/E (B/S) junction - LGate scaling reduces base width of parasitic bipolar Tx + Higher doping concentration and steeper profile increase base Gummel number, thus reducing current gain of parasitic bipolar Tx + Scaling/thinning of Si film reduces B/E (B/S) junction area • Reduced-VT leakage contained w.r.t. increased FET current drive + Lower VDD results in lower VBody + Lower body factor in scaled high-performance low-VT Tx

  9. Hysteretic VT Variation • Long time constants for body charging & discharging • Impact ionization current • Junction leakage/current • GIDL • Body potential during switching transient determined primarily by • External biasing • Capacitive coupling • Charge imbalance through switching cycle • Circuit behavior depends on prior states and switching patterns

  10. PD SOI Device States • Equilibrium states • Quiescent states with DC leakage balances in and out of body • 1st vs 2nd switches • Dynamic state • Device is randomly switched without relation to a timing reference • Steady-state • Device activity and duty cycle fixed and repetitive • Body voltage make excursion between repeated potentials • Body charges gained/lost through switching cycle equal to zero

  11. 1st Switch vs 2nd Switch • Pre-switch body voltage • 1st switch : Balance of back-to-back D/B and B/S diode • 2nd switch : D/B capacitive coupling • Early generations of PD/SOI technologies (e.g. 0.25/0.18 m) • High diode balance voltage due to high VDD • Higher pre-switch body voltage and faster delay for 1st switch • Scaled PD/SOI technology • Low diode balance voltage due to low VDD • Increased D/B capacitive coupling due to high doping concentration and steep doping gradient • Higher pre-switch body voltage and faster delay for 2nd switch

  12. Hysteresis in PD SOI CMOS Circuits • Large delay disparity at beginning due to different initial states • VBS determined by balance of forward diode current & reverse leakage • VBS determined by capacitive coupling • Steady-state independent of initial states • Determined only by Q through switching cycle • Reached when Q through switching cycle equal to zero • Steady-state delay can be outside the bound of the two initial-state delays • Circuit family dependent (e.g. pass-Tx based ckts highly hysteretic) PD/SOI CMOS Inverter 1.8 V, Leff = 0.145 µm, Wp/Wn = 2, 1.0 ns Period, 50% Duty Cycle, 100 ps Input Slew Initial Input at “Low” (L-H) / ”High” (H-L) (M. M. Pelella et al., VLSI-TSA, 1999)

  13. Ckt Simulation & Static Timing with Floating Body Devices • Convergence of initial DC solutions • Initial DC potential of floating nodes determined by charging of associated capacitances by small leakage currents with long time constants • Solution : Scale down all capacitance values by a large factor (e.g. 10-12 orders of magnitude) during initial DC solution phase  Solution convergence improved by same factor • Steady-State • Prohibitively long simulation time reach steady-state • Solution: Fast dynamic equilibrium methodology which computes Q in the single cycle which defines the periodic patterns & use iterative algorithm to predict body voltages  Over 2 orders of magnitude improvement in simulation time (* I. Aller & K. E. Kroell., IEEE Int. SOI Conf., 1999) • Static timing • State diagram based body voltage estimation and bounding (* K. L. Shepard & D. J. Kim., ICCAD, 1999)

  14. Thermally-Assisted Impact Ionization in SOI Device • Onset of I-V kink well below Si bandgap (Eg 1.2 eV) • At low VDD, lattice temp. becomes driving force for impact ionization • Significantly enhanced by self-heating in thin Si film in scaled SOI device (P. Su et al., IEEE Int’l SOI Conf., 2001/2002)

  15. VT,lin • PD/SOI devices designed with higher VT,lin than bulk CMOS • As drain voltage is raised, body voltage goes up, causing VT to decrease • Higher VT,lin necessary to maintain adequate VT,sat to contain leakage • Higher VT,lin degrades performance and/or noise margin • Circuits where devices spend substantial amount of time in linear region during switching transient • Pass-gate (especially nMOS/pMOS-only pass-gate) • Stack devices • SRAM read/write pass transistor • Low VDD operation • Full transmission-gate • Replace nMOS/pMOS-only pass-gate • Not practical for SRAM read/write pass-transistors

  16. VT,lin in Scaled PD SOI Devices • Optimum PD/SOI devices design alleviates higher VT,lin requirement • Match Ioff to bulk CMOS at shortest Leff at operating temperature • Allows higher Ioff (lower VT,sat ) at nominal Leff ( PD/SOI device has better short-channel roll-off) • Scaling VDD  Decrease in VT,sat due to floating body effect becomes less due to reduction in electric field induced impact ionization (E. Leobandung et al., IEDM, 1998)

  17. Scaling/Thinning of Si Film • Reduced junction capacitance • Performance improvement • Decreases disparity between 1st and 2nd switch • Lower pre-switch body voltage for 2nd switch due to reduced D/B capacitive coupling • Better short channel roll-off • Better soft error rate (SER) • Less charge generation/collection volumn • Reduced junction area for parasitic bipolar Tx

  18. Scaling/Thinning of Si Film • Increase body resistance • High distributed RC renders body contact less effective and eventually useless • More severe self-heating • Dynamic full-depletion (or quasi-depletion) for tSi < 40/50 nm • Body becomes fully-depleted under certain bias condition and/or during certain circuit switching transient • Unified PD/FD device model with seamless transition • Modeled by varying the built-in potential between B/S junction, thus changing amount of body charges the B/S diode can sink for a given change in body potential • Circuit simulation and static timing methodology • Body voltage bounds established based on partial depletion need to be extended • Occurs first in long-channel, low-VT device • In short-channel device, proximity of HALO increases effective body doping  less likely to be dynamically fully-depleted

  19. Fully-Depleted (FD) SOI Devices • Channel depletion layer extends through the entire Si film • Significantly reduces (or completely eliminates) floating-body effect • Raised S/D to reduce series resistance BOX ( B. Doris et al., IEDM, 2002)

  20. VT Setting of FD SOI Devices • Highly-doped channel • Traditional P+/N+ poly • VT sensitive to Si film thickness variation • Mobility degradation and junction edge tunneling leakage • Amount of dopant required can not be realistically achieved for ultra-thin body • Lightly-doped or undoped channel • VT set by S/D Halo or by use of mid-gap gate material • Reduce VT sensitivity to Si film thickness variation • Reduce dopant fluctuation effect • Reduce transverse electric filed and impurity scattering  Higher mobility • Reduce band-to-band tunneling at junction edge • Use of mid-gap material allows the use of a single electrode for both nMOS and pMOS

  21. Advantages of FD SOI Devices • Thin Si film leads to • Better gate control of channel charges  Better subthreshold slope • Channel leakage limited by Si film  Reduced subthreshold leakage • Reduced junction capacitance (A. Vandooren et al., IEEE Int’l SOI Conf., 2002)

  22. FD SOI Device and Design Considerations • Fringing electric field from S/D penetrates into buried oxide underneath the channel • Causes back interface virtual biasing, resulting in degraded ubthreshol leakage and slope • Can be suppressed by thinning the buried oxide at the expense of larger junction capacitance to the substrate • FD SOI quite “transparent” for design migration, challenges primarily in technology development and manufacturing (A. Vandooren et al., SOI Conf., 2002; J. G. Fossum et al., SOI Conf., 2002)

  23. Tunneling Current in Thin Gate Oxide • tox scaled with L to maintain gate control, VT , and performance • Oxide tunneling leakage increases over 30X per generation (2.5X/0.1 nm) • Ioff increases by 3X – 5X per generation • High-k gate dielectric needed beyond tox = 1.0 nm (E. J. Nowak et al., IBM J. R&D, March/May, 2002) (T. Ghani et al., Symp. VLSI Tech., 2000)

  24. Tunneling Current in Thin Gate Oxide • ECB : Electron tunneling from conduction band HVB : Hole tunneling from valence band EVB : Electron tunneling from valence band • EVB generates substrate current • Significantly less than tunneling current from gate to channel • Bulk CMOS : effect can usually be neglected (W. C. Lee & C. Hu, Symp. VLSI Tech., 2000) (S. K. H. Fung et al., IEDM, 2000)

  25. Gate Oxide Tunneling Current in PD SOI Device • Substrate (body) current due to EVB charges/discharges body, thus changing VT and affecting circuit operation • Performance and noise margin • Increases disparity between 1st switch and 2nd switch • Cause (or “aid”) dynamic full-depletion of body Igb BOX

  26. Effect of Igb : Initial Quiescent State • Igb changes strength of individual Tx in quiescent state, thus affecting circuit delays when circuit switches • Effect more pronounced at lower temperature (C. T. Chuang et al., SSDM, 2001) (R. V. Joshi et al., Symp. VLSI Tech., 2001)

  27. Power4 Path Count vs % Change of Path Delay • 170 M Tx, 1.1 GHz, 115W, 64b PowerPC • 1.5 V, 0.18 m PD/SOI Technology with 7 Levels of Cu • Leff = 0.075 m, tox = 2.3 nm, tSi = 150 nm, tBOX = 145 nm • Presence of Igb : 4% slow-down to 6% speed-up at 85o C (C. T. Chuang et al., SSDM, 2001)

  28. Impact of Igb on PD SOI CMOS Ckt Performance • 1.5V, 0.18 m PD SOI technology with tox = 2.3 nm • Inverter : 9.5% slow-down to 15% speed-up • Power-4 critical paths : 4% slow-down to 6.0% speed-up • 34 Kb Z-Series L1 directory SRAM : 6% write performance degradation, less for read • 1.2V, 0.13m PD SOI technology with tox = 1.5 nm • Single-ended LEAP circuit : 11% slow-down to 2.5% speed-up • Dual-rail CPL circuit : 13% slow-down to 9.5% speed-up • 1st cycle latch set-up time : 12% - 20% degradation

  29. Effect of Igb : 1st Switch vs 2nd Switch • 1st switch : V (G, S, D) = (0, 0, VDD), VBody = VDiode,cut-in , • Igb: No appreciable effect on pre-switch Vbs • 2nd switch : V (G, S, D) = (VDD, 0, 0), VBody = 0 • Igb: Charge up body, increasing pre-switch Vbs • Disparity between 1st/2nd switch increases as Igb increases • High-k gate dielectric and thinner Si film improve performance and reduce 1st/2nd switch disparity 1st Switch 2nd Switch (S. K. H. Fung et al., IEDM, 2000)

  30. Effect of Igb : Full-Depletion • Accumulation mode (e.g. pass-gate configuration with S/D at “High”) represents ultimate criteria of “full-depletion” • In accumulation mode, electrons tunnel to the body, recombine with holes, thus can potentially cause (or “aid”) full depletion of the body (H. Wan et al., IEEE Int’l SOI Conf., 2002)

  31. Gate Leakage Reduction in UTB SOI & DG Devices • Reduced vertical electric field • Undoped (or lightly-doped) body : Qdepl  0 • Quantum confinement in ultra-thin Si film • Lower electric field at bottom of inversion layer • 3X-4X (over 10X for high-k) gate leakage reduction (L. Chang et al., IEDM, 2001)

  32. Self-Heating • Thermal conductivity of buried oxide (1.4 W/m-oC) about 2 orders of magnitude lower than Si (120 W/m-oC)  Local self-heating • Concerns for devices that are on most/all the time • Biasing elements, current source/mirror, bleeder, etc. • Circuits with high duty cycle and slow slew rate such as clock distribution, I/O drivers, etc. • Self-heating enhances thermally-assisted impact ionization at low voltage • Thermal coupling in adjacent fingers/devices • Scaling of Si film significantly degrades thermal resistance • Phonon boundary scattering • Phonon confinement

  33. Thermal Coupling in Adjacent Fingers/Devices • Bell-shaped spatial temperature distribution with characteristics width determined by thermal diffusion length in Si (in sub-0.5 m range) • Overlap of spatial temperature distributions from individual active fingers significantly increases effective Rth • Saturation occurs when distance between center/far-away fingers approaches characteristics width of bell-shaped curve • Scaled technology  smaller/tighter groundrules saturation occurs at higher number of active fingers  more significant Rth increase 0.18 m PD/SOI, tungsten local interconnect, 7 layer of Cu (R. V. Joshi et al., SISPAD, 2001)

  34. Phonon Boundary Scattering • When tSi phonon mean free path (300 nm at room temperature)  Phonon boundary scattering causes significant increase in Rth • Increase particularly significant for thin Si film on thick buried oxide (M. Ashegi et al., IEEE Int’l SOI Conf., 2002)

  35. Phonon Confinement • When tSi phonon wavelength (tens of nm)  Phonon confinement • Boundary conditions changes from usual periodic boundary conditions for bulk materials to essentially zero displacements on the boundaries in SOI • Group velocities damped with higher modes having lower group velocities • In 10 nm Si quantum well, thermal conductivity falls to 13% of its bulk value • Dispersion curves for shear modes in 10-nm silicon quantum well (A. Balandin and K. L. Wang, Physical Review B., Vol. 58, No. 3, pp. 1544-1549, 1998)

  36. Soft Error Rate (SER) • -generated charges in SOI substantially less than in bulk CMOS • Appreciable charge collection only when -particle hits channel region • Total charge collected at cell storage node can be significantly higher than - generated charges due to parasitic bipolar effect • Scaled PD/SOI • Charge generation volume decreases • Qcrit decreases due to reduced storage node capacitance & reduced VDD • Parasitic bipolar gain decreases • Thin Si film reduces charge generation volume & B/E (B/S) junction area of parasitic bipolar Tx (P. Oldiges et al., Symp. VLSI Tech., 2002)

  37. Strained-Si Channel on SOI • Lattice mismatch results in biaxial tensile strain • Increases subband splitting, thus reducing intervalley scattering • Reduces conductivity effective mass, thus enhancing carrier transport • Single strained Si layer improves both n-FET and p-FET • Surface channel - advantage in device scaling • Gate oxide formed on silicon • Complements enhanced mobility (improved ION) of strained-Si channel device with the benefit of SOI (S. Takagi et al., J. Appl Phys., 1996, p. 1567; R. Oberhuber et al., Phys. Rev. B, 1998, p. 9941.)

  38. Strained-Si Channel on SOI: Design Implications • Narrower bandgap of SiGe causes heterostructrual band offset • Reduces VT and increases Ioff • Disparity in mobility enhancement between nMOS/pMOS • May upset  (n/p strength) ratio while migrating existing designs • “Biaxial” tensile strain • Mobility enhancement the same along X- and Y-axis • Disparity in mobility enhancement for “bent gate” at 45o angle • Higher junction capacitance • SiGe layer has 7% higher dielectric constant and 10% lower built-in potential due to narrower bandgap • Higher body doping to compensate for VT reduction • Thermal conductivity 15X lower than Si  more severe self-heating • Floating body effect (FBE) • Larger recombination current at B/S junction due to higher ni caused by narrower bandgap of SiGe  reduces FBE • Larger band-to-band tunneling and trap-assisted tunneling current at D/B junction due to narrower bandgap, higher dielectric constant of SiGe, and higher body doping  increases FBE

  39. High-k Gate Dielectric • Lower bandgap than SiO2 • Must be thicker to contain tunneling leakage • Charge-trapping-related VT instability and mobility degradation • Higher gate capacitance per unit area • Some circuit resizing/retuning may be necessary, especially in critical paths where device capacitances dominate (J. Robertson, J. Vacuum Science & Tech. B, May/June 2000, p. 1785; H. Iwai et al., IEDM, 2002)

  40. Integration of High-k Gate & Strained-Si Channel • HfO2 on Si : mobility severely degraded w.r.t. SiO2 on Si • Strained-Si + HfO2 (at Eeff = 1.4 MV/cm) • 30% higher mobility than SiO2 on Si • 60% higher mobility than HfO2 on Si (K. Rim et al., Symp. VLSI Tech., 2002)

  41. Summary • CMOS scaling bounded by non-scalable physical limitations • Sustained improvement in performance and density require introduction of new device structures and materials • PD SOI has extended VLSI performance while introducing design complexity caused by parasitic bipolar effect and hysteretic VT variations • FD SOI represents a logic extension of planar device structure • Gate dielectric tunneling, self-heating, and single-event upset present new design challenges • Strained-Si channel and high-k gate dielectric are examples of new materials to enhance CMOS device performance

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