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Implementation of parity bit generator/checker

Implementation of parity bit generator/checker. - Kavyashree Pilar. Project proposal. Implemen t ation of parity bit generator and checker circuit. Project d eliverables : Schematic Worst case timing analysis Power and thermal analysis

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Implementation of parity bit generator/checker

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  1. Implementation of parity bit generator/checker -KavyashreePilar

  2. Project proposal Implementation of parity bit generator and checker circuit. Project deliverables: Schematic Worst case timing analysis Power and thermal analysis Hardware implementation and functionality verification.

  3. Background • Random data generator: Pseudo-Random noise generator circuit • Parity bit generator : Generates a logic high parity bit when odd number of data bits are on logic high state. • Channel : Represents noisy environment which can alter one or more data bits and the parity bit. • Parity checker: Generates a new parity bit using the data bits and compares it with the parity bit received with data.

  4. Components used ICs used: 74AC164 : 8 bit shift register 74AC86 : Quad 2-input ExOR gate PCB Board Specification: Standard board : 10mils thick with copper routing layers on top and bottom.

  5. Schematics

  6. Termination resistors and bypass capacitors Trise_min= 3ns F_knee = 166.66MHz AC coupling capacitor value = 100pF Length of rising edge(L) = 21.347” L/4 = 5.3368” Longest trace length ~ 5” No termination required

  7. Timing analysis • PNR data generator • tPLH of U1 = 12.5ns • tPLH of U2 = 10.8ns • Q5-Ex-or input = 0.7025 • Ex-or output – B = 0.7025 • Setup time for U1= 2.5ns • Minimum clock period = 27.205ns • Maximum operating frequency =36.76MHz

  8. Worst Case Power and thermalAnalysis U1: 74AC164 Each output drives 2 ExOR gate inputs Q5 and Q6 drive one more ExOR gate CPD= 150pF, Ci = 10pF, assume f = 36MHz Vcc=5.5V,Ic=3mA Pd = 234.3mW θJA = 700C/W Junction temperature = 51.4010 C MTBF is very good – No cooling required.

  9. Power and thermal Analysis - Continued • All ExOR gates except U5 drive 4 ExOR inputs • Cpd = 57pF • Icc= 80uA • Ci = 10pF • Pd= 53.256mW • θJA = 700C/W • Junction temperature = 38.7280C • U5 drives 3 Ex-OR inputs: • Pd = 47.8115mW • Junction temperature = 38.34680C

  10. Next steps • Hardware implementation • Functionality testing: • Verification of parity bit generation circuit • Verification of parity checker circuit

  11. Learning PCB design using OrCAD capture/CIS and PCB editor. Issues faced and solutions: ORCAD capture – schematic done V6.6 demo version can not be modified with V6.3. Demo version can handle only upto 60 components. The following command can be used on command prompt can be used when netlist generation via GUI fails: C:\Cadence\SPB_16.3\tools\capture\pstswp -pst -d "<filename>.DSN" -n "allegro" -c "C:\Cadence\SPB_16.3\tools\capture\allegro.cfg"

  12. Learning - continued • CMOS design – analyze termination requirements before starting with the schematics.

  13. References Datasheets: CD74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE - Texas Instruments CD54/74AC164, CD54/74ACT164 8-Bit Serial-In/Parallel-Out Shift Register - Texas Instruments Thermal conductivity information http://www.ti.com/lit/an/spra953b/spra953b.pdf PCB Design : “Capture CIS Tutorial” - EkaratLaohavaleeson “Layout Editor Tutorial” - Jordan Bisasky http://www.cis.gvsu.edu/~kurmasz/Teaching/OldCourses/CS451/General/WebPage/ReferenceDocuments/Switches/switches.html

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