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Figure 3.1 Digital logic technologies .

This series of figures provides an overview of digital logic technologies, including PLAs, FPLDs, and CPLDs. It also showcases different package types and architectures, such as the MAX 7000 and FLEX 10K. Learn about the use of lookup tables and how FPGAs are implemented in silicon wafers.

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Figure 3.1 Digital logic technologies .

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  1. Figure 3.1 Digital logic technologies.

  2. Figure 3.2 Digital logic technology tradeoffs.

  3. Figure 3.3 Using a PLA to implement a Sum of Products equation.

  4. Figure 3.4 Examples of FPLDs and advanced high pin count package types.

  5. Figure 3.5 MAX 7000 macrocell.

  6. Figure 3.6 MAX 7000 CPLD architecture.

  7. Figure 3.7 FLEX 10K100 FPLD die photo, PIA interconnects are visible.

  8. Figure 3.8 FLEX 10K Logic Element (LE).

  9. Figure 3.9 Using a lookup table (LUT) to model a gate network.

  10. Figure 3.10 FLEX 10K Logic Array Block (LAB).

  11. Figure 3.11 FLEX 10K CPLD architecture.

  12. Figure 3.12 Silicon wafer containing XC4010E 10,000 gate FPGAs.

  13. Figure 3.13 Single XC4010E FPGA die showing 20 by 20 array of logic elements and interconnect.

  14. Figure 3.14 Xilinx 4000 Family Configurable Logic Block (CLB).

  15. Figure 3.15 CAD tool design flow for FPLDs.

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