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Microprocessor System Design Memory Timing

Microprocessor System Design Memory Timing. Omid Fatemi (omid@fatemi.net). Outline. Reading / Writing memory Timing requirements - microprocessor side Timing of 6264 and 2764 Slow memories and wait states DRAM interfacing RAS / CAS signals DRAM in PC. Writing. Sequence of steps

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Microprocessor System Design Memory Timing

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  1. Microprocessor System DesignMemory Timing Omid Fatemi (omid@fatemi.net)

  2. Outline • Reading / Writing memory • Timing requirements - microprocessor side • Timing of 6264 and 2764 • Slow memories and wait states • DRAM interfacing • RAS / CAS signals • DRAM in PC

  3. Writing • Sequence of steps • Setup address lines • Setup data lines • Activate write line (maybe a pos edge) • Usually latch on the next edge

  4. Writing

  5. Reading • Steps • Setup address lines • Activate read line • Data available after specified amt of time

  6. Reading

  7. Processor Timing Diagramfor any memory read machine cycle

  8. Processor Timing Diagramfor any memory write machine cycle

  9. Chip Select • Usually a line to enable the chip

  10. Minimum Mode

  11. Minimum Mode When Memory is selected?

  12. Minimum Mode 220 bytes or 1MB

  13. When interfacing memory chips to a microprocessor, consider the following: • TAVDV – address access time • TRLDV – read access time • TDVWH – memory setup time • TWHDX – data hold time • TWLWH – write pulse witdth Refer to 8088 data manual

  14. Address Access Time (TAVDV)

  15. Timing Requirements during Memory Read • TAVDV • 3TCLCL – TCLAV – TDVCL • Address Access Time • from Address is Valid to Data is Valid

  16. Read Access Time (TRLDV)

  17. Timing Requirements during Memory Read • TRLDV • 2TCLCL – TCLRL – TDVCL • Read Access Time • from Read Signal is Low to Data is Valid

  18. Memory Setup Time (TDVWH)

  19. Timing Requirements during Memory Write • TDVWH • 2TCLCL – TCLDV +TCVCTX • Memory Setup Time • from Data is Valid to Write Signal is High

  20. Data Hold Time (TWHDX)

  21. Timing Requirements during Memory Write • TWHDX • TCLCH – X • Data Hold Time (after WR’) • from Write Signal is High to Data is Invalid (Inactive)

  22. Write Pulse Width / Write-Time (TWLWH)

  23. Timing Requirements during Memory Write • TWLWH • 2TCLCL – Y • Write Pulse Width / Write-Time • from Write Signal is Low to Write Signal is High

  24. 8088 MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS

  25. Computation of Timing Requirements for 8088 using a 4Mhz Clock • TAVDV • 3TCLCL – TCLAVmax – TDVCLmin • 3(250 ns) – 110 ns – 30 ns • 610 ns • TRLDV • 2TCLCL – TCLRLmax – TDVCLmin • 3(250 ns) – 165 ns – 30 ns • 555 ns

  26. 8088 MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS

  27. Computation of Timing Requirements for 8088 using a 4Mhz Clock • TDVWH • 2TCLCL – TCLDVmax +TCVCTXmin • 2(250 ns) – 110 ns + 10 ns • 400 ns • TWHDX • TCLCH – X • 118 ns – 30 ns • 88 ns • TWLWH • 2TCLCL – Y • 2(250 ns) – 60 ns • 440 ns

  28. Timing Requirements for 8088 using a 4Mhz Clock • TAVDV = 610 ns • TRLDV = 555 ns • TDVWH = 400 ns • TWHDX = 88 ns • TWLWH = 440 ns

  29. Can we interface a 6264 to the 8088 chip which uses a 4MHz clock?

  30. Timing Requirements for 6264 SRAM • TAVDV = ? • TRLDV = ? • TDVWH = ? • TWHDX = ? • TWLWH = ?

  31. HM6264B Series Read TIMING REQUIREMENTS

  32. HM6264B Series Write TIMING REQUIREMENTS

  33. HM6264B Series Read Timing Diagram

  34. HM6264B Series Write Timing Diagram

  35. Timing Requirements for 6264 SRAM • TAVDV = tAA • TRLDV = tOE • TDVWH = tDW • TWHDX = tDH • TWLWH = tWP

  36. Timing Requirements for HM6264B-8L • TAVDV = tAA = ? • TRLDV = tOE = ? • TDVWH = tDW = ? • TWHDX = tDH = ? • TWLWH = tWP = ?

  37. HM6264B Series Read TIMING REQUIREMENTS

  38. HM6264B Series Write TIMING REQUIREMENTS

  39. Timing Requirements for HM6264B-8L • TAVDV = tAA = 85 ns • TRLDV = tOE = 45 ns • TDVWH = tDW = 40 ns • TWHDX = tDH = 0 ns • TWLWH = tWP = 55 ns

  40. Comparing Timing Requirements of 8088 (using 4 Mhz clock) and HM6264B-8L

  41. Can we interface a 2764 to the 8088 chip which uses a 4MHz clock?

  42. Timing Requirements for 2764 EPROM • TAVDV = ? • TRLDV = ? • TDVWH = ? • TWHDX = ? • TWLWH = ?

  43. M2764A Read Mode AC Characteristics

  44. M2764A Read Mode Timing Diagram

  45. Timing Requirements for 2764 EPROM • TAVDV = tAVQV • TRLDV = tGLQV • TDVWH = N/A • TWHDX = N/A • TWLWH = N/A

  46. Timing Requirements for 2764 EPROM • TAVDV = tAVQV = ? • TRLDV = tGLQV = ? • TDVWH = N/A • TWHDX = N/A • TWLWH = N/A

  47. M2764A Read Mode AC Characteristics

  48. Timing Requirements for M2764A-3 • TAVDV = tAVQV = 180 ns • TRLDV = tGLQV = 65 ns • TDVWH = N/A • TWHDX = N/A • TWLWH = N/A

  49. Comparing Timing Requirements of 8088 (using 4 Mhz clock) and M2764A-3

  50. What if we need to interface a “slow” memory to the 8088?

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