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EELE 414 – Introduction to VLSI Design

EELE 414 – Introduction to VLSI Design. Module #7 – Storage Devices Agenda Sequential Logic Memory Announcements Read Chapters 8 & 10. Sequential Logic.

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EELE 414 – Introduction to VLSI Design

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  1. EELE 414 – Introduction to VLSI Design Module #7 – Storage Devices • Agenda • Sequential Logic • Memory • Announcements • Read Chapters 8 & 10

  2. Sequential Logic • Sequential Logic- Now we move to logic circuits whose outputs depend on: - the current values of the inputs - the past values of the inputs- this is the definition of "Sequential Logic"- in order to make logic circuits based on the previous values of inputs, we need a storage device

  3. Feedback & Metastability • Feedback- consider this circuit- the outputs are "fed back" to the inputs- this gives the following relationships: Q = Vin1' Qn = Vin2' Vin1 = Qn Vin2 = Q Vin1 = Vin2' = Q' = Vin1 Vin2 = Vin1' = Qn' = Vin2 - this circuit will HOLD or STORE a logic value- feedback gives us the ability to build "Sequential Storage Devices"

  4. Feedback & Metastability • Metastability- what if the input is VDD/2- in an ideal world, the outputs would be driven to VDD/2- we know that noise exists in the world (thermal, shot, etc…)- noise will add a small Δv to the nodes in the system

  5. Feedback & Metastability • Metastability- let's consider a + Δv being superimposed on input Vin1 who starts out at VDD/2 - this causes a - Δv to be superimposed on output Q due to the inverting nature of the inverter- this - Δv is fed back to input Vin2, which in turn causes a + Δv on output Qn VDD/2 - Δv VDD/2 + Δv VDD/2 - Δv VDD/2 + Δv

  6. Feedback & Metastability • Metastability- this new + Δv is fed back to the original Vin1 voltage in an additive nature- this drives Vin1 even further positive, which in turn starts the loop all over again- this feedback loop continues until the inputs and outputs are driven to either a 0 or a 1 VDD/2 - Δv - Δv VDD/2 + Δv + Δv VDD/2 - Δv - Δv VDD/2 + Δv + Δv

  7. Feedback & Metastability • Metastability- Metastability is the situation where the inputs cause an indeterminate output in a feedback circuit - i.e., VILmax < Vin < VIHmin- using feedback, we know that the circuit will always be driven to a final state- this is also called a "Bi-Stable" element meaning that the inputs and outputs will be driven to one of two final states (i.e., a 1 or a 0)- the final state that the circuit is driven to is unknown, but we know it will go there eventually

  8. Feedback & Metastability • Recovery time- manufactures can specify the maximum amount of time that a bi-stable element will take to reach its final value- the time that the output is unknown is called the "Metastability Region"- the time it takes to exit the Metastable region is called the "Recovery Time" (trecovery)

  9. SR Latch • SR Latch- consider the following circuit which is called an "SR Latch"- To understand the SR Latch, we must remember the truth table for a NOR Gate:AB F 00 1 01 0 10 0 11 0

  10. SR Latch • SR Latch- when S=0 & R=0, it puts this circuit into a Bi-stable feedback mode where the output is either:Q=0, Qn=1 Q=1, Qn=0AB FAB F 00 1 (U2) 00 1 (U1) 01 0 01 0 (U2) 10 0 (U1) 10 0 11 0 11 0 0 0 0 1 1 0 0 1 1 0 0 0

  11. SR Latch • SR Latch- we can force a known state using S & R:Set (S=1, R=0)Reset (S=0, R=1) AB FAB F 00 1 (U1) 00 1 (U2) 01 0 01 0 (U1) 10 0 (U2) 10 0 11 0 (U2) 11 0 (U1) 0 1 1 0 0 1 1 0 0 1 1 0

  12. SR Latch • SR Latch- we can write a Truth Table for an SR Latch as followsS R Q Qn . 0 0 Last Q Last Qn - Hold 0 1 0 1 - Reset 1 0 1 0 - Set 1 1 0 0 - Don’t Use- S=1 & R=1 forces a 0 on both outputs. However, when the latch comes out of this state it is metastable. This means the final state is unknown.

  13. SR Latch • SR Latch- Remember the Truth Table for an SR Latch: S R Q Qn . 0 0 Last Q Last Qn - Hold 0 1 0 1 - Reset 1 0 1 0 - Set 1 1 0 0 - Don’t Use- there is delay associated with changes on the input causing a change on the outputs: tPLH(SQ) = Δt for a LOW-to-HIGH transition on S to cause an output change on Q tPHL(RQ) = Δt for a HIGH-to_LOW transition on R to cause an output change on Q- there is also a specification on how small of a pulse width we can have and be recognizedtPW(min) = minimum input pulse width that can be recognized

  14. SR Latch • SR Latch- Just as in the NOR gate transistor circuit, the delay comes from charging and discharging capacitance.- However, in addition to the intrinsic capacitance of the driving NOR gate and the receiver’s gate capacitance, the driver must also drive the gate capacitance of its own bi-stable element

  15. S'R' Latch • S’R’ Latch- we can also use NAND gates to form an inverted SR LatchS’ R’ Q Qn . 0 0 1 1 - Don’t Use 0 1 1 0 - Set 1 0 0 1 - Reset 1 1 Last Q Last Qn - Hold

  16. SR Latch w/ Enable • SR Latch w/ Enable- this allows us to add an enable line also using NAND gates- remember the Truth Table for a NAND gateAB F 00 1 - a 0 on any input forces a 1 on the output 01 1 - when C=0, the two EN NAND Gate outputs are 1, which forces “Last Q/Qn” 10 1 - when C=1, S & R are passed through INVERTED 11 0

  17. SR Latch w/ Enable • SR Latch w/ Enable- the truth table then becomesC S R Q Qn . 1 0 0 Last Q Last Qn - Hold 1 0 1 0 1 - Reset 1 1 0 1 0 - Set 1 1 1 1 1 - Don’t Use 0 x x Last Q Last Qn - Hold

  18. D Latch • D Latch- a modification to the SR Latch where R = S’ creates a D-latch- when C=1, Q <= D- when C=0, Q <= Last ValueC D Q Qn . 1 0 0 1 - track 1 1 1 0 - track 0 x Last Q Last Qn - Hold

  19. D Latch • D Latch- we can use CMOS transmission gates to implement the functionality of a D-latch

  20. D Latch • D Latch- The T-gates operate as complementary switches which either: - drive the output - hold the input - the T-gate gives the necessary functionality and a reduced transistor count in the final implementation - timing specifications dictate how long before and after the clock that the data must be valid in order for the circuit to operate correctly

  21. D Latch • D Latch- An edge triggered D-latch can be created using the following configuration:

  22. Flip Flops • Flip-Flops- a "Latch" is a device that "tracks or holds" the input depending on a control signal (i.e., C or CLK)- a "Flip-Flop" is a device that will "acquire and hold" the input when a transition is present on C or CLK- Flip-Flops are commonly used in sequential logic due to their speed- The general configuration of a Flip-Flop has two latches in series called Master and Slave stages

  23. D-Flip-Flops • D-Flip-Flops- we can combine D-latches to get an edge triggered storage device (or flop) - the first D-latch is called the “Master”, the second D-latch the “Slave”MasterSlave CLK=0, Q<=D “Open” CLK=0, Q<=Q “Close” CLK=1, Q<=Q “Closed” CLK=1, Q<=D “Open” - on a rising edge of clock, D is “latched” and held on Q until the next rising edge

  24. D-Flip-Flops • D-Flip-Flops- In CMOS, we can use two of the T-gate stages to implement a falling edge D-flip-flop with a minimal transistor count

  25. D-Flip-Flops • D-Flip-Flops- The DFF passes and holds the information on D to Q on the falling edge of CK

  26. D-Flip-Flops • D-Flip-Flops- The DFF requires tsetup and thold to be met in order for proper operation- The following shows a setup/hold violation

  27. D-Flip-Flops • D-Flip-Flops- the CMOS DFF can be implemented in a regular layout pattern just as combinational logic

  28. D-Flip-Flops • D-Flip-Flops- the bi-stable behavior of Sequential Logic can be used to create hysterisis.- this can be used to overcome intermittent switching of digital circuits in a noisy environment.- Hysterisis creates a gate which has a different switching threshold for rising edges and a different switching threshold for falling edges.- the following is an example of such a circuit called a Schmitt Trigger.

  29. Memory • Memory- Memory is the storage of digital information- Memory is typically classified differently than flip-flops and latches due to the ability to create large arrays of storage- Memory is actually the driving force behind Moore's law and consumes the majority of area and power in a modern uP- The factors that drive the different architectures we see in memory are: 1) Cost - cost per bit, more bits per area reduces cost 2) Speed - how fast can we get or put data, does this match the performance needs of other logic 3) Power Consumption - does the power consumption make deep memory infeasible

  30. Memory • Memory Types Notes on definitions: 1) The word "RAM" is now used interchangeably with R/W memory. Formally, most types ROM are also Random Access 2) ROM memory typically refers to storage that can't be written during program execution. It can hold program and data information, but under normal operation a CPU doesn't use it for variable storage. As Flash EEprom gets faster and more reliable, Flash may become used as RAM

  31. Memory - SRAM • Static Random Access Memory (SRAM)- SRAM is volatile memory (i.e., if the power is removed, the information is lost)- SRAM uses an inverter loop to store the digital information- two NMOS transistors acting as switches are used to Read and Write the stored data- we call the circuitry to store 1-bit a "cell"

  32. Memory - SRAM • SRAM Addressing- we configure the cells into an array- we address each cell using:Row Address - a row decoder produces a "Word Line" - this gives a "Row Select" (RS) signalColumn Address - a column decoder produces a "Bit Line" - this gives a "Column Select" (CS)

  33. Memory - SRAM • SRAM Addressing- The Word Lines are used to address a row of cells- The Bit Lines are used to address a column in addition to reading and writing- There are two bit lines per cell, BL and BL' - This allows a difference amplifier to be used to distinguish between a 1 and a 0

  34. Memory - SRAM • SRAM Reading- The capacitance of the Bit Lines can be very large due to multiple cells being attached- This creates a problem during a READ because the small cell will need to drive this large capacitance- To reduce the amount of charge that the cell has to drive during a READ, pull-up transistors are used to "pre-charge" the lines to VDD

  35. Memory - SRAM • SRAM Reading- In order to design a usable SRAM cell, we must meet the condition that: "Reading the value does NOT destroy the contents of the cell"- Let's look at what happens during a read to see how to meet this conditionReading a '0'- Initially V1=0v, V2=VDD - M3 and M4 are turned ON - this allows the Cell to drive BL and BL' - The voltage V2 will be the same as the pre-charged BL' line, so no current will flow through M4

  36. Memory - SRAM • SRAM ReadingReading a '0' cont… - M1 will attempt to pull down the BL line through the M3 and pull-up transistors.- This action creates a slight difference between BL and BL' which gives us the information about the cell (i.e., it holds a 0). WLBLBL' VDD 0 VDD 0 VDD 0

  37. Memory - SRAM • SRAM ReadingReading a '0' cont… - The BL line will actually pull up V1 through the M3 transistor- we need to ensure that V1 does not get large enough to turn ON M2- if V1>VT,n-M2, then M2 will begin conducting current and will put the cell into an unknown state- our first design condition is:

  38. Memory - SRAM • SRAM ReadingReading a '0' cont… - We can write KCL at the V1 node to derive an expression between the size ratio of M3 and M1 in order to meet our condition. - We can then substitute in V1=VT,n

  39. Memory - SRAM • SRAM ReadingReading a '0' cont… - We can then rearrange to put in terms of Transconductance- since the NMOS mobility's and Oxide Capacitances are the same, we get

  40. Memory - SRAM • SRAM ReadingReading a '0' cont…- Due to symmetry, we size M3=M4 and M1=M2.- In addition, the Lengths of all transistors are typically the same- this allows us to relate the sizes for 4 of the 6 transistors in the SRAM cell

  41. Memory - SRAM • SRAM Writing- when writing to the SRAM cell, we inject full swing digital signals onto BL and BL'. - when we assert the Word Lines, M3 and M4 will open and attempt to change the state of the cell.- the worst case situation is when writing a '0' when a '1' is already stored in the cell- another design condition is that when we put full swing voltage levels on BL and BL', we need to be able to change the state of the cell.Writing a '0'- Initially V1=VDD, V2=0v (i.e., the cell stores a '1')- we write a 0 by driving BL=0, BL'=VDD- when the Word Line is asserted, M3 and M4 are turned ON

  42. Memory - SRAM • SRAM WritingWriting a '0' cont…- In this case, BL'=VDD and V2=~0v. If we met our first design condition, then BL' should NOT be able to change the state of the cell- In order to successfully change the state of the cell, V1 must be driven low enough by BL to turn OFF M2.- this gives us our 2nd design condition for the SRAM cell during a write:

  43. Memory - SRAM • SRAM WritingWriting a '0' cont… - We can write KCL at the V1 node to derive an expression between the size ratio of M3 and M5 in order to meet our condition. - Substituting in V1=VT,n and rearranging, we get:

  44. Memory - SRAM • SRAM WritingWriting a '0' cont…- the Oxide Capacitances are the same so we get:- Due to symmetry, we size M5=M6- now we have a relationship for all 6 transistors in the SRAM cell- Note: these ratios enable DC operation. In order to determine the final sizes of the transistors, we use timing or area specifications.

  45. Memory - SRAM • SRAM Operation- The voltages on BL and BL' will look as follows during successive Read/Write cycles Write 1 Read 1 Write 0 Read 0 WLBLBL' VDD 0 VDD 0 VDD 0

  46. Memory - SRAM • SRAM Read Circuitry (Sense Amps)- Sense Amplifiers are used to distinguish between a 0 and a 1 on BL / BL'- The first stage amplifier is a current amp that is enabled using a PSAE' signal- The output of this amp is fed into a voltage amplifier which amplifies the signals to full swing CMOS levels (DIO, DIO')

  47. Memory - SRAM • SRAM Write Circuitry- To write a value, a high strength digital buffer is used to drive BL and BL'- The buffer has to be strong enough (i.e., Low Zout) to drive all of the capacitance on the Bit Lines within a specified time.

  48. Memory - SRAM • SRAM Operation- Waveforms of a Read and Write cycle READ WRITE

  49. Memory - SRAM • SRAM Layout- SRAM cells can be laid out in a very compact manner. This allows them to be easily copied to form large arrays. 1 Cell 4x4 Array

  50. Memory - DRAM • Dynamic Random Access Memory (DRAM)- A volatile memory storage device even smaller than SRAM- DRAM uses a capacitor to store the value of the digital information (instead of an inverter loop)- one NMOS transistor is used to address the storage element- the one-transistor configuration is known as a “1T” DRAM

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