Introduction to Partial Reconfiguration

1. Introduction to Partial Reconfiguration Adam Flynn EEL 4930/5934 4/11/08

2. Agenda • Introduction • Definitions and Acronyms • Potential Implementations • Example Applications • Demo

3. Introduction • Full Reconfiguration • Bitfile for entire FPGA is loaded onto FPGA • Partial Reconfiguration (PR)? • Only certain portion(s) of FPGA are reprogrammed • Advantages • Shorter reconfiguration time • Less power • Smaller bitfiles • Rest of FPGA can remain operational • Few applications outlined later

4. Definitions and Acronyms • Partial Reconfiguration Module (PRM) • Design module that is swapped in and out on the fly • Partial Reconfiguration Region (PRR) • Section of FPGA fabric set aside for a PRM. • A single PRR can have multiple PRMs defined for it • Base Design • Static portion of the design – everything that’s not a PRM and remains operational during PR • Bus Macro • Pre-placed, pre-routed macro that locks routing between PRMs and the base design • How PRM communicates with rest of FPGA

5. Potential Application FPGA Module A Base (Static) Region PRR Module C PR Region Bus Macros Module B • Apply to what we’ve done so far in class … • Modules A, B, C are memory map, register file, controller, etc … • PRR is Fibonacci Calculator or Accumulator • Can reconfigure FPGA to implement any function • Provided function is amenable to standard interface

6. BM 3 Pad PR Implementation #1 • Static section controls PRR, provides interface to system • Access to I/O must go through bus macro Static Configuration\Communication Controller Single Reconfigurable Module = Bus macros I/O

7. Module #1 Configuration\ Communication Controller Module #3 Module #2 Module #4 PR Implementation #2 Smallest Reconfigurable Wiring Biggest

8. Module #1 Configuration\ Communication Controller Module #2 PR Implementation #3

9. Application A • Embedded system where FPGA must constantly communicate with system • Mission critical modules can maintain real-time links while the functionality of other portions of the FPGA are reconfigured • Not possible with full reconfiguration • Reconfiguring PRRs can allow FPGA to … • Implement alternate video coding standard • Use different radio link protocol/frequency • Provide hardware acceleration for several kernels too large to fit onto FPGA simultaneously

10. “sockets” for modules Application B • Fault Tolerance • Useful for FPGAs in harsh environments (i.e. space) • Configuration bits can become corrupted • Adaptable Component-level Protection • Level of Fault Tolerance/Protection can be reconfigured • See figure for visualization • Configuration Scrubbing • “Configuration Manager” monitors configuration bits, corrects corrupted bits Component- level Adaptation B A B A D B BLANK A BLANK C no parallel, SCP 2× parallel, SCP no parallel, TMR 4× parallel, single SIFT – Software-Implemented Fault Tolerance SSCP – Spatial Self-Checking Pair TSCP – Temporal Self-Checking Pair SNMR – Spatial N-Mod Redundancy TNMR – Temporal N-Mod Redundancy ABFT – Algorithm-Based Fault Tolerance

11. Application C • Multipurpose System Design • Idea: Create high level design with several PPRs • PRRs can be [re]populated as application requirements are defined/change • Provides flexibility • Does not require designer to anticipate future upgrades

12. Acknowledgements • Chris Conger, Ross Hymel • Borrowed heavily from previous presentations

13. Demo