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Progress Report Flash ADC Probabilistic Architecture

Progress Report Flash ADC Probabilistic Architecture. Yuta Toriyama. yuta@ee.ucla.edu August 10, 2012. The design of a variability-agnostic Flash ADC Using small devices and low supply voltages for a low-power low-area design

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Progress Report Flash ADC Probabilistic Architecture

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  1. Progress ReportFlash ADC Probabilistic Architecture Yuta Toriyama yuta@ee.ucla.edu August 10, 2012

  2. The design of a variability-agnostic Flash ADC Using small devices and low supply voltages for a low-power low-area design Architecture / calibration techniques to deal with large amounts of variation Basic concept: Model each comparator as having a static voltage offset at its input Low Power Flash ADCs

  3. Probabilistic Approach • Architectural design: • Allow only certain comparators to be active • Turn off power to unused comparators • Requirements: • Threshold values and indexes of chosen comparators must be monotonically increasing • Single 1 output to decoder 1 0 X 0 1 0 0 0 1 X 0 Logic Encoder X 0 0 0 X 0

  4. Represent the entire Flash architecture as a network Each comparator (or voltage at which it switches) is a node Network Formulation

  5. Any path from lowest to highest comparator in this network guarantees a monotonic sequence of active comparators To find an “optimum” path, assign weights to each edge Network Formulation

  6. LP Formulation & Simplex Algorithm x = vector s.t. xi{edge chosen (1), edge not chosen (0)} LP can be solved with Simplex Algorithm Theoretical average-case complexity = O(|V|*|E|) maximize cTx s.t.Ax = [1 0 0 . . .-1]T 0 ≤ xi ≤ 1, i 1 2 3 4 5 6 1 -1 0 0 0 0 1 0 -1 0 0 0 1 0 0 -1 0 0 1 0 0 0 -1 0 1 0 0 0 0 -1 0 0 0 1 -1 0 0 0 0 1 0 -1 0 1 0 -1 0 0 0 1 0 0 -1 0 0 1 0 0 0 -1 0 0 1 0 -1 0 0 0 1 0 0 -1 0 0 0 0 1 -1 = A nodes arcs

  7. Dijkstra’s Algorithm Solves single-source shortest path problem for networks with non-negative edge weights Simple implementation complexity = O(|V|2) Balls (vertices) connected by strings (edges) of different lengths (weights)

  8. FPGA Implementations Dijkstra’s Algorithm: outperforms Simplex in time-to-solution uses much fewer resources in FPGA implementation than an implementation of the Simplex algorithm

  9. Edge Weight Assignment Calculate the noise power contribution of each arc: Vj Ck = for allk= {1,2,Numarcs} Vi di= 4 • Allows for the inclusion of non-uniform distributions • Does not take into account linearity

  10. Look-Up Table Currently the encoder output indicates the index for which comparator was toggled Instead, we would like the output to indicate what analog voltage trips the comparators Threshold voltages known from DAC measurements taken for foreground calibration

  11. Look-Up Table Add a look-up table at the output of encoder Values filled in after calibration Size of memory required ~1kb for # comparators = 1024 (based on number of active comparators after calibration)

  12. New Graph Formulation Divide threshold voltage axis into L equally-spaced regions Find one comparator from each region, index of comparators still must be monotonically increasing Cost = distance from midpoint of each region

  13. New Graph Formulation ENOB, linearity improved

  14. Conclusion • Dijkstra’s Algorithm leads to great improvement in calibration method • LUT-based calibration shows vast improvement in linearity over previous network formulation method

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