1 / 20

October 3, 2014

CS@APU: CS400 Compiler Construction. CS400 Compiler Construction. Sheldon X. Liang Ph. D. October 3, 2014. Azusa, CA. 1. October 3, 2014. Azusa Pacific University, Azusa, CA 91702, Tel: (800) 8 25-5278 Department of Computer Science, http://www.apu.edu/clas/computerscience/.

tamas
Télécharger la présentation

October 3, 2014

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CS@APU: CS400 Compiler Construction CS400 Compiler Construction Sheldon X. Liang Ph. D. October 3, 2014 Azusa, CA 1 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  2. Code generation: front-end and back end CS@APU: CS400 Compiler Construction • Front-end and back-end are generalized terms that refer to the initial and the end stages of a process. The front-end is responsible for collecting input in various forms from the user and processing it to conform to a specification the back-end can use. The connection of the front-end to the back-end is a kind of interface (IR). • Many programs are divided conceptually into front and back-ends, but in most cases, the "back-end" is hidden from the user. However, sometimes programs are written which serve simply as a front-end to another, already existing program, such as a graphical user interface (GUI) which is built on top of a command-line interface. 2 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  3. CS@APU: CS400 Compiler Construction Keep in mind following questions • Back End Code Generation • Hidden from user • Directly face machine • IR, interface between FE & BE • Instruction set and selection • IR to assembly • Criteria • CISC vs RISC • Code Generation • For expressions • Post-order traversal • Why post order? 3 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  4. Code generation CS@APU: CS400 Compiler Construction • Our book's target machine: • opcodesource1, source2, destination • add r1, r2, r3 • addI r1, c, r2 • loadI c, r2 • load r1, r2 • loadAI r1, c, r2 // r2 := *(r1+c) • loadAO r1, r2, r3 • i2i r1, r2 // r2 := r1 (for integers) • cmp_LE r1, r2, r3 // if r1<=r2, r3:=true, else r3:=false • cbr r1, L1, L2 // if (r1) goto L1, else goto L2 • jump r1 • Symbols: @x represents x's offset from the sp 4 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  5. Code generation CS@APU: CS400 Compiler Construction • Let's start with some examples. • Generate code from a tree representing x = a+2 - (c+d-4) • Issues: • which children should go first? • what if we already had a-c in a register? • Does it make a difference if a and c are floating point as opposed to integer? • Generate code for a switch statement • Generate code forw = w*2*x*y*z 5 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  6. Code generation CS@APU: CS400 Compiler Construction • Code generation = • CISC vs RISC • instruction selection • instruction scheduling • register allocation 6 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  7. CISC vs RISC Architecture CS@APU: CS400 Compiler Construction 7 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  8. CISC vs RISC Architecture CS@APU: CS400 Compiler Construction 8 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  9. Instruction selection CS@APU: CS400 Compiler Construction • IR to assembly • Why is it an issue? • Example: copy a value from r1 to r2 • Let me count the ways... • Criteria • How hard is it? • Use a cost model to choose. • How about register usage? 9 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  10. Instruction selection CS@APU: CS400 Compiler Construction • How hard is it? • Can make locally optimal choices • Global optimality is NP-complete • Criteria • speed of generated code • size of generated code • power consumption • Considering registers • Assume enough registers are available, let register allocator figure it out. 10 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  11. Instruction scheduling CS@APU: CS400 Compiler Construction • Reorder instructions to hide latencies. • Example: ( ) loadAI $sp, @w, r1 ( ) add r1, r1, r1 ( ) loadAI $sp, @x, r2 ( ) mult r1, r2, r1 ( ) loadAI $sp, @y, r2 ( ) mult r1, r2, r1 ( ) loadAI $sp, @z, r2 ( ) mult r1, r2, r1 ( ) storeAI r1, $sp, @w memory ops : 3 cycles multiply : 2 cycles everything else: 1 cycle 11 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  12. Instruction scheduling CS@APU: CS400 Compiler Construction • Reorder instructions to hide latencies. • Example: • (1) loadAI $sp, @w, r1 • (4) add r1, r1, r1 • (5) loadAI $sp, @x, r2 • (8) mult r1, r2, r1 • (9) loadAI $sp, @y, r2 • (12) mult r1, r2, r1 • (13) loadAI $sp, @z, r2 • (16) mult r1, r2, r1 • (18) storeAI r1, $sp, @w (1) loadAI $sp, @w, r1 (2) loadAI $sp, @x, r2 (3) loadAI $sp, @y, r3 (4) add r1, r1, r1 (5) mult r1, r2, r1 (6) loadAI $sp, @z, r2 (7) mult r1, r3, r1 (9) mult r1, r2, r1 (11) storeAI r1, $sp, @w (13) 12 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  13. Instruction scheduling CS@APU: CS400 Compiler Construction • Reorder instructions to hide latencies. • Example2: (1) loadAI $sp, @x, r1 (4) mult r1, r1, r1 (6) mult r1, r1, r1 (8) mult r1, r1, r1 (10) storeAI r1, $sp, @x 13 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  14. Instruction scheduling CS@APU: CS400 Compiler Construction • Reorder instructions to hide latencies. • We need to collect dependence info • Scheduling affects register lifetimes ==> different demand for registers • Should we do register allocation before or after? • How hard is it? • more than one instructions may be ready • too many variables may be live at the same time • NP-complete! 14 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  15. Register allocation CS@APU: CS400 Compiler Construction • Consists of two parts: • register allocation • register assignment • Goal : minimize spills • How hard is it? • BB w/ one size of data: polynomial • otherwise, NP-complete • based on graph coloring. 15 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  16. Code generation CS@APU: CS400 Compiler Construction • Generating code for simple expressions • If the expression is represented by a tree, a post-order walk gives an evaluation sequence  Why post-order? • Changing the evaluation sequence may result in code that uses fewer registers. • Idea: find out how many registers are needed for each subtree and evaluate the most expensive one first. • Consider the following algorithm that labels tree nodes with the number of registers needed (for the ILOC architecture): 1 if n is a left leaf, or right leaf and variable 0 if n is a right leaf and constant max(labellchild, labelrchild) if labellchild labelrchild labellchild +1 if labellchild == labelrchild label(n) = 16 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  17. Code generation CS@APU: CS400 Compiler Construction • Generating code for simple expressions • The idea behind our algorithm: • Variables need to be loaded in registers, so leaves need one register • For rhs constants we can use opI operations, so no extra register needed • If we need k registers for each subtree, we'll use k for the left one, keep 1 for the result, and then use another k for the right subtree. That's a total of k+1 registers • If we need k registers for one subtree and m<k for the other, then use k for the one subtree, keep the result in 1, use the remaining k-1 (which is at least m) for the other subtree. That's a total of k registers. • When generating code, make sure to evaluate the most expensive subtree first. 17 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  18. Code generation CS@APU: CS400 Compiler Construction • Generating code for expressions • What if an expression contains a function call? • Should the compiler be allowed to change the evaluation order? • Big idea #1 wrt to optimizing or moving code around : Be conservative! • Generating code for • boolean operators • relational operators read the book • array references 18 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  19. CS@APU: CS400 Compiler Construction Got it with following questions • Back End Code Generation • Hidden from user • Directly face machine • IR, interface between FE & BE • Instruction set and selection • IR to assembly • Criteria • CISC vs RISC • Code Generation • For expressions • Post-order traversal • Why post order? 19 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

  20. CS@APU: CS400 Compiler Construction Thank you very much! Questions? 20 October 3, 2014 Azusa Pacific University, Azusa, CA 91702,Tel: (800) 825-5278 Department of Computer Science,http://www.apu.edu/clas/computerscience/

More Related