Signal and Design Integrity April 2002

1. Signal and Design IntegrityApril 2002

2. Technical issues in Deep Sub-Micron Design • Manufacturability (Chip can’t be built) • Antenna rules • Minimum area rules for stacked vias • CMP (Chemical Mechanical Polishing) area fill rules • Signal Integrity (failure to meet Performance targets) • Crosstalk induced errors • Timing dependence on crosstalk • IR Drop on power supplies • Substrate coupled noise • Design Integrity (reliability failures in the field) • Electromigration on power supplies • Hot electron effects on devices • Wire self heat effects on clocks and signals

3. Why now? • These effects have always existed, but become worse at deep sub-micron sizes because of: • Finer geometries • Greater wire and via resistance • Higher electric fields (if supply voltage not scaled) • More metal layers • Higher ratio of cross coupling to grounded capacitance • Lower supply voltages • More current for a given power • Lower device thresholds • Smaller noise margins • Good news: Same solutions that work at 150 nm and 130 nm will work for next few technology generations until << 100 nm

4. Crosstalk induced errors • Transition on an adjoining signal causes unintended logic transition • Symptom - chip fails (repeatably) on certain logic operations Aggressor net Coupling C Victim net Wire R Drive R Grounded C Input Noise Tolerance

5. Timing Dependence on Crosstalk • Timing depends on behavior of adjoining signals • Symptom - Timing predictions inaccurate compared to silicon. Effect can be large: 3:1 on individual nets. Delay here and here depends on the behavior of other nets Wire R Grounded C Coupling C (multiplied by Miller effect) Other logic net(s)

6. Effect of Crosstalk on Delay Thresholds min nom max nominal friendly unfriendly

7. Electromigration • Power supply lines fail due to excessive current • Symptom: Chip eventually fails in the field when the wire breaks Currents depend on driver type, loads, and how often cell is switched Currents depend on currents of other cells Power supply network consists of wires of varying sizes; they must be big enough, but too big wastes area Pad Current limit depends on wire size

8. IR Drop • Voltage drop in supply lines from currents drawn by cells • Symptom: chip malfunctions on certain vectors • Biggest problem - what’s the worst case vector? Currents depend on driver type, loads, and how often cell is switched Voltages depend on currents of other cells Allowable voltage drop at pin Power supply network consists of wires of varying sizes; they must be big enough, but too big wastes area Pad

9. Hot Electron Effects • May also be called short channel effect • Caused by extremely high electric fields in the channel • Occurs when voltages are not scaled as fast as dimensions • Effect becomes worse as devices are turned on harder • Symptom: Thresholds shift over time until chip fails Oxide and/or interface is damaged here Gate +++ +++ N+ diffusion Electrons pick up speed in channel; ‘hot’ electrons are the fastest of a statistically fast bunch Impact ionization occurs here

10. Hot Electron Effect (cont) Contours of constant hot electron flux • Depends on how hard device is driven (input slew rate) • And on the size of the load Vgs Trajectory with large C, fast Tin Trajectory with small C, slow Tin Vds

11. Wire Self Heat • May also be called signal wire electromigration • Wire heats above oxide temperature as pulses go through • Symptom: Chip eventually fails when wire breaks • Depends on metal composition, signal frequency, wire sizes, slew rates, and amount of capacitance driven • Requires different data/formulas from power supply EM Oxide Metal

12. Package Substrate Noise • Currents injected by high speed switching of digital devices • Supply currents injected via substrate contacts

13. Crosstalk Supply Noise Vdd2 Vdd1 “0” Charge Sharing Gnd2 Leakage Supply Noise Gnd1 Analog Noise in Custom Digital ICs Propagated Noise Overshoot (TDDB) CLK Undershoot (TDDB)

14. What can tools do about these problems? • Accurate Analysis • Make sure real problems are caught • Avoid fixing problems that aren’t really there • For analog issues, such as substrate noise, this is about all we can do. The user must decide how to fix the problem • Tools can try to prevent or avoid errors • Tools can try to fix errors once they have been found • Can view two ways • For a given problem (ie. crosstalk) what can each tool do? • For a given tool (ie. synthesis), which problems can be alleviated? • Following slides have a mixture of these analyses.

15. Signal Integrity Flow- Full Chip Design Floor Planning Place & Route Chip Assembly All Tools Verification • Signal Integrity Correction and Checking: • Early and Often throughout the design flow • Fewer Signal Integrity issues at the end of the design flow Design global wiring Build Blocks Re-verify Re-verify Sign-off Do global routing -Signal nets correct by construction -Push budgets into blocks -Place blocks -Place cells with Optimization - Re-check loads, drives, timing -implement wiring strategy -Route with variable width, spacing, shielding -Re-extract routing parasitics -Re-check loads, drives, timing -Re-extract routing parasitics - Re-check loads, drives, timing

16. Crosstalk • Prevention • Shielded • Routing • Automatic • Repeater • Insertion • Power: • -PGP • -EM • -IR Drop • Signal • Self Heat • Crosstalk • Delay • Wire/Clk • Self Heat • Clk • Self Heat • Signal Hot • Electron • Power: • EM & • IR Drop • Clk Hot • Electron • Crosstalk • Parasitics • Power • Driven Timing Delay Calc Logical Simulation Floor Planning Placement & Optimization Clock Tree Parasitic Extraction Routing New Library Data Signal Integrity Flow- Block Design • Signal Integrity issues fixed at each step in the Design Flow: • Post-Route • Crosstalk • Fixing

17. Controlling crosstalk • Use timing windows • Use a sensitivity-based noise check to minimize false failures • Need fast analysis with SPICE-like distributed models • Based on reduced order models • Automatically fix functional noise failures via ECOs to P&R • Support mixed flat and hierarchical analysis • Special commands for fixing post-route crosstalk • Needed for good flow convergence

18. Timing Windows for Crosstalk • Only consider signals that can change at the same time • Data comes from static timing analysis One clock cycle B D STA Timing Windows A C Crosstalk Magnitudes Worst case occurs here, does not include signals A or D.

19. IN 0UT Glitch Rejection • Calculates the sensitivity of each receiver to noise at its input • Accounts for the inherent glitch rejection of each receiver • Depends on input waveform, input circuitry, and output load Noise sensitivity is dependent on input waveform shape and output loading

20. DC Noise Peak Vs Noise Immunity • Using Sensitivity analysis (such as CeltIC) implies less rework!

21. Crosstalk Analysis – Accuracy Measurement • Can reduced order models give accurate results? • Worked through this with customers – it’s very difficult • To determine error budget, need to understand each portion separately • Need to get LEF, TLF, and SPICE to exactly agree • Need to run, and measure, SPICE simulations • Slopes, normally a second order effect, are first order for crosstalk checking • Even SPICE analysis has ambiguities: • Simultaneous Switching (SS) vs. Worst Case Alignment (WCA)

22. Simultaneous switching is not worst delay Thresholds min nom max nominal friendly unfriendly

23. Crosstalk results – lumped vs distributed • Glitch Noise • Lumped analysis was about (-10%, +70%) for noise peak. • CeltIC (distributed analysis) was (-9%, +4%) for noise peak • Since most signals fail by only a few millivolts, using distributed analysis results in many fewer reported errors.

24. Glitch size with lumped model

25. Celtic (distributed) Noise Errors (note scale change)

26. Better prevention helps flow convergence • Crosstalk prevention in synthesis • Upgrade drivers of slow transition signals even if not needed for timing • Global slew limits • Clock tree generator should include EM prevention for clocks • Crosstalk prevention in routing • Long parallel line avoidance • Longer term, track assignment does even better • Takes advantage of ‘free’ shielding by power supply grid • Crosstalk timing prevention in synthesis (forward prediction)

27. Fixing errors after routing • Fixing crosstalk errors after routing requires care • Rip-up-and-reroute may change neighbors • Making victims stronger makes them better aggressors • Specific post-route heuristics are required for best convergence • Insert/change components with minimal routing changes • Change some marginal components preemptively to avoid iterations • These commands are also useful for other post route changes • ECOs

28. Strategy for Crosstalk Fixing • From Post Route Analysis • Create repair files for Post Route Crosstalk Fixing • Apply repair file • Buffer insertion • Wide Space Routing • Shielded Routing Wide Space Routing Buffer Insertion Shielded Routing

29. Timing Convergence • Extremely few timing problems from crosstalk glitch fixing (none in 20-30 large examples at 0.15 and 0.13 micron) • If flow is timing driven, critical path has strong drivers, short nets and good slopes -> few crosstalk problems • Conversely, nets with problems tend to be long nets with weak drivers, and buffer insertion helps these. • Wire fixes (extra spacing/shielding) increase performance if anything

30. Handling Timing Impact of Crosstalk • Correct treatment of coupling has an effect even if there is no noise! • Need accurate analysis of effect • Lumped models have large errors • Distributed analysis is needed • Reduced order models give good results • Would like to avoid the need to iterate around timing windows

31. victim in Even without noise, coupling is important What existing timing verifiers see. Real circuit on silicon Logic 0 Solid 0 victim in True timing is about 15% faster

32. Crosstalk results – lumped vs distributed • Analysis of crosstalk induced delay • Lumped analysis was about (-20%, +450%) on delay • Spice has simultaneous switching; Lumped analysis used Worst Case Alignment • The delay measurement was interconnect delay – not stage delay • A distributed analysis with reduced order models (CeltIC) was (-16%, +10%) for delay

33. Lumped crosstalk delay

34. Distributed (CeltIC) Delay Errors

35. Start SDF SDF SDF TW TW End Noise Aware-Timing • Internal iteration CeltIC Noise Aware Timer STA

36. Avoids iteration between tools Noise Aware Timing Static Timing Analysis Detailed Crosstalk Delay Calculation

37. Signal Integrity (SI) in Synthesis • Synthesis with placement can help SI issues • Crosstalk and EM prevention in placement/sizing • Interface to detailed crosstalk analysis • Generate timing windows, constraints, and clocks • Generate maximum frequency for reliability checks • Wire self heat and hot electron • Post routing crosstalk correction • Add buffers • Size drivers • Decision based on routing and cell congestion • Includes post route timing corrections • Integrated clock tree generation supports EM prevention

38. Signal Integrity Avoidance in Synthesis • Other possible prevention options • Global slew limit (can limit length as a function of driver size) • Global length limits (per layer). • Some customers have requested this for manufacturability, but it can also be used for SI. • Better correction options • Decide bigger driver, inserted buffer, or extra spacing on a net by net basis after routing.

39. Controlling Wire Self Heat (also called Signal Line Electromigration or Joule Heating) • Need a maximum frequency for each net • Timing analysis and/or synthesis can provide this • Generated by propagating clocks forward to data signals • Maximum frequency, times load, gives maximum possible current • Clock nets are a particular concern • Highest frequency operation, long wires, big loads • Worst spot on net may not be at driver • Vias may have tighter limits • Specialized clock drivers may only have pins on the high metal layers, leading to a good initial clock route, but…. • Router may change layers during rip-up and re-route • Nets must be tapered (to reach pins), but only at input pins

40. All wiring segments, vias, and cell I/O pins must be checked • Frequency dependent Cload and/or Slew are calculated and checked. • EM current density change on a wire path are measured and checked. OK 4M No Good Buffer Buffer OK

41. Signal Line Electromigration • New Placement and Routing features • Router must taper correctly (No taper at driver) • Analysis must check correctly • Tapered (input) pins are not checked • All segments on net are checked • All vias on the net are checked. • Layers and vias that are in the routing rule, but not used, are not checked.

42. Extract Improvements Needed for SI • Accuracy for cross coupling • Capacity • Coupling capacitance reduction

43. Extraction for Cross Coupling • Fully distributed coupling reflects physical reality • Files are huge (3GB for 100K instances) -> 300GB for 10M cells • Need a reduction that reduces network size with an acceptable degradation of accuracy. • We believe a good compromise is possible here. • When combined with delay calculation, can potentially regain ~15% timing margin associated with assuming coupling Cs are truly grounded.

44. Intelligent Network Reduction A very small example 6 shapes 9 inter-shape couplings • SPICE/DSPF require even more components • No native element for distributed RC • 12 Rs, 9 Cs for T model, • 6 Rs, 16Cs for Pi model • Net result: huge files

45. Network Reduction (continued) • Reduce number of components • Preserve important properties • Preserve moments (Elmore delay and higher order) • Preserve cross-coupling properties

46. Hot Electron Degradation • Most customers are designing their libraries such that the CAD tools don’t need to check this. • If needed, can be fixed by a combination of timing analysis and placement, and pre-characterization of cells • Timing analyzer computes input slope and max frequency • Placement tool computes output load, then consults pre-characterized table • If load is too high for specified chip lifetime, upsizes driver or inserts isolation buffer

47. Power Supply Analysis • IR drop analysis • Static (uses average current) • Dynamic (worst case stimulus) • Most users use static analysis since worst case vectors are unknown. • This is an active research problem • Important to do this early in the flow since widening the power supplies later causes huge routing problems.

48. Power Calculation Flow Average Design -LEF, DEF Power Characterization Supply Voltages RSPF parasitics VCD file or freq +activity Triplet Power Calc Vectors PWL Power Spec File

49. Rail Analysis Flow Design: LEF, DEF • Extract Power network • Calculate IR Drop and EM through wire segments • Display on physical design SEDSM Rail Analysis Wire Seg File Cell Seg File

50. Rail Analysis