SCE-MI 2.0, Cadence Summary (Accellera ITC Meeting)

1. SCE-MI 2.0, Cadence Summary(Accellera ITC Meeting) Feb 17, 2005

2. * SCE-MI CPD has been investigated and proven by Cadence in the context of customers’ verification systems SCE-MI CPD Meets ITC Stated Goals* • Support for Variable-Length Messages (VLMs) • Eases task of writing BFMs • Enables SCE-MI infrastructure to optimize transport of VLMs • Eliminate Uncontrolled Clock • Eases task of writing BFMs • Backward Compatibility • Maintain SCE-MI 1.0 functionality, 1.0 & 2.0 BFMs can coexist • Maintain focus on performance

3. SCE-MI 1.0 SCE-MI CPD assign messageWordOut = mQ[currMessageWord]; assign transmitLast = (transmitReady && (currMessageWord == lastMessageWord)); always @(posedge uclock) begin if (readyForCclock == 0) begin if (outReceiveReady) begin readyForCclock <= 1; outTransmitReady <= 0; end else if (cclockEnabled) begin if (newMessageGenerated) begin currMessageWord <= 0; transmitReady <= 1; end if (outReceiveReady == 0) readyForCclock <= 0; else begin if (transmitLast) transmitReady <= 0; if (transmitReady) begin currMessageWord <= currMessageWord + 1; end end end assign messageWordOut = mQ[currMessageWord]; assign transmitLast = (transmitReady && (currMessageWord == lastMessageWord)); always @(posedge cclock) begin if (newMessage) begin currMessageWord <= 0; transmitReady <= 1; newMessage <= 0; end end Always @(posedge cclock) begin if (transmitLast) transmitReady <= 0; if (transmitReady) currMessageWord <= currMessageWord + 1; end Native VLM Support Simplifies BFM • VLM macro eliminates clock control • Interaction of multiple message ports compounds problem in 1.0

4. SCE-MI CPD SCE-MI 1.0 SW Side SW Side HW Side HW Side Native VLMs Enable Higher Performance • SCE-MI Infrastructure can optimize VLM transport • Multiple message words transferred across HW/SW interface in one operation • Hardware-Side (Emulator) handles message segmentation for input ports, aggregation for output ports

5. * These characteristics are embodied in the Cadence-Proposed Draft (CPD) and Cadence’s implementation of same SCE-MI 2.0: Desirable Characteristics • Language Neutrality • C/C++ • Synthesizable Verilog/VHDL/SystemVerilog • Platform Neutrality • Simulation/Acceleration, Event-Based/Cycle-Based • Support Ease-of-Use/Performance trade-off • SCE-MI 1.0/2.0 compatibility and co-existence allows selection of appropriate mechanism

6. SCE-MI proxy macro proxy macro Language Neutrality • SCE-MI CPD maintains SCE-MI language neutrality TLM RTL TLM C/C++ TLM C/C++ SW Side HW Side • Abstract proxies easily created for SW-side (e.g. TLM) • Standard RTL on HW-side supported by a broad range of vendors and applications

7. Platform Neutrality • Use of CPD macros eliminate the need for clock control • Unbounded “Zero-Time Operations” do not exist Sim Kernel wait() schedService() serviceLoop() SW Side HW Side • SW side and HW side run in a single-process simulation

8. 1.0/CPD Compatibility • CPD macro semantics can be defined in terms of 1.0 macros • Ease support for SCE-MI 1.0 vendors • Ensure compatibility of 1.0/CPD semantics ClockNum=N Cclock Clock ClockNum=N TransmitReady TransmitReady SceMiClockPort TransmitLast ReceiveReady ReadyForCclock Message Message w w+1 SceMiMessageOutPort SceMiClockControl SceMiVarMessageOutPort

9. Streaming for Performance • Steaming allows longer free-run times in emulator • Slightly modified isReady semantics enable streaming • Applicable to non-reactive tests Deferred isReady SW Side 3 isReady HW Side

10. SCE-MI CPD Incremental Improvement

11. SCE-MI CPD Exceeds ITC Stated Goals • Support for Variable-Length Messages (VLMs) • Eliminate Uncontrolled Clock • Backward Compatibility • Platform Neutrality • Streaming Capable for Performance