1 / 13

superscalars

superscalars. Lalitha Ramadoss Elec 6200 Computer Architetcure& Design Lectured by Dr.Vishwani Agrawal Electrical&computer Engineering Auburn. What is a superscalar processor?. Execute more than one instruction in each cycle Exploits Instruction level parallelism

tave
Télécharger la présentation

superscalars

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. superscalars Lalitha Ramadoss Elec 6200 Computer Architetcure& Design Lectured by Dr.Vishwani Agrawal Electrical&computer Engineering Auburn

  2. What is a superscalar processor? • Execute more than one instruction in each cycle • Exploits Instruction level parallelism • Motivation is Pipelining+Parallelism • Better performance • IBM RS/6000, TI SuperSPARC, the HP PA7100, and the DEC AXP 21064

  3. Simple superscalar INT IF ID MEM WB FP

  4. Advanced Superscalars WB INT MEM IF ID FP WB MEM IF ID IF ID Lw/sw MEM WB

  5. Instruction Level Parallelism • Increasing the depth of pipeline to overlap more instructions-number of stages increased • Replicating the internal components-multiple issue technique

  6. Superscalar History • Cray CDC 6600-1965 • Intel i960CA-1988,AMD-29000(1990)-RISC • P6 PentiumPro and PentiumII,Intel80386-CISC • Power PC970

  7. Superscalar concepts • Scheduling • Issues • Execution • Speculation • WriteBack • Retirement or Completion

  8. Superscalar Classification • Static Superscalars-execute instructions in program order • Dynamic Superscalars-execute instructions out of order • Dynamic with Speculation-ability to speculate on branches

  9. Data Dependencies and Hazards • Output Dependency MUL R1, R4, 15 ; R1 = R4 * 15 ADD R2, R1, 1 ; R2 = R1 + 1 MOVE R1, R3 ; R1 = R3 • Antidependency ADD R1, R2, 1 ; R1 = R2 + 1 MOVE R2, R3 ; R2 = R3

  10. Dynamic multiple issue processors • Scheduling by Hardware lw $t0,20($s2) add $tl,$t0,$t2 sub $s4,$s4,$t3 • Dynamic Pipeline scheduling

  11. Dynamic scheduled Processors IF&ID RS RS RS RS FP Int Int FP Commit unit

  12. References • Computer Organization&Design Patterson Hennessy-2 & 3 edition • http://www.cs.swan.ac.uk/~csneal/HPM/superscalar.html • http://en.wikipedia.org/wiki/Superscalar • http://www.ipp.mpg.de/de/for/bereiche/stellarator/Comp_sci/CompScience/csep/csep1.phy.ornl.gov/ca/node25.html

More Related