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Lect 5: Instruction Encoding and Instruction Set

Lect 5: Instruction Encoding and Instruction Set. T T T T T T T T. T T T T T T T T. mod TTT r/m. 7. 7. 0. 0. d32| 16 | 8 | none. data32 |16 |8 | none. 7 6 5 3 2 0. 7 6 5 3 2 0. ss index base. “mode r/m” byte. “s-i-b” byte. address displacement. immediate data. opcode

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Lect 5: Instruction Encoding and Instruction Set

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  1. Lect 5: Instruction Encoding and Instruction Set

  2. T T T T T T T T T T T T T T T T mod TTT r/m 7 7 0 0 d32| 16 | 8 | none data32 |16 |8 | none 7 6 5 3 2 0 7 6 5 3 2 0 ss index base “mode r/m” byte “s-i-b” byte address displacement immediate data opcode (one or two bytes) (T represents an opcode bit.) register and address mode specifier Instruction Encoding General Instruction Format

  3. Encoding of Operand Length Field • w Field Operation Size Operation Size • During 16-bit During 16-bit • Data Operations Data Operations • 0 8 Bits 8 Bits • 1 16 Bits 16 Bits Encoding of reg Field When w Field is not present in Instruction

  4. Encoding of 16-bit Address Mode with “mod r/m” Byte

  5. Encoding of 32-bit Address Mode with “mod r/m” Byte (no ‘s-i-b’)

  6. Encoding of 32-bit Address Mode( “mod r/m” byte and “s-i-b” byte present): * Important Note: When index field is 100, indicating no index register, then ss field MUST equal 00. If index is 100 and ss does not equal 00, the effective address is undefined.

  7. Encoding the instruction in Machine code • Example: • MOV BL, AL ; MOV opcode byte: 100010dw • d = 0 REG field is source; w =1 for word operation; mod r/m = 11 011; REG = 000 • First byte : 10001000 (88H); Second byte: 11 000 011 (C3H) • ADD [BX][DI]+1234H, AX; ADD opcode byte : 000000dw • d=0 REG field is source; w =1 for word operation; mod r/m = 10 001; REG = 000 • First byte : 00000001 (01H); Second byte: 10 000 001 (81H) • Resulting Machine code: 01813412H • MOV ECX,2 ; MOV opcode byte: 1011w reg (immediate to reg short form) MOV AX,[EBX+2*ECX] MOV opcode byte: 1000101w (reg/mem to reg) • MOV ECX,2 ; 1011 1 001 (B9H) 0000 0010 0000 0000 0000 0000 0000 0000 • MOV AX, [EBX+2*ECX] • First byte : 10001011 Second Byte: 00 000 100 Third byte: 01 001 011 mod REG r/m ss index base • The Resulting Machine code: 8B044B • Address size prefix : 01100111 (67) ; Operand size prefix: 01100110 (66) • The Result: 66 | B9 00000002 67 | 8B 04 4B

  8. 80386 Instruction Set • 80386 base instruction set encoding table: See Fig 4.5 • Instruction Types • General Data Transfer • Arithmetic/Logic • Shift/Rotate • Bit test and bit scan • Flag Control • Control Transfer • String handling • System Control • Data Transfer Instructions • MOV : 8 instructions ; operation: (dest) ¬ (src), Flags Affected: none • MOV AX,[BP] 10001011 01 000 110 0000 0000 mod reg r/m displacement • There are several machine codes to represent one MOV instruction. The assembler must choose an efficient one. • MOVSX: sign-extend MOVSX EBX, AX (reg from reg/mem) • MOVZX: zero-extend MOVZX CX, DATA (reg from reg/mem)

  9. General Data Transfer • XCHG operation (dest) « (src) ; flags affected : none • reg/mem with reg, reg with accumulator (short form) • XCHG AX,DX • XLAT : Translate String ; operation (AL) ¬ ((AL)+(BX)) ; flags affected: none • Load Effective Address and Load Pointer Instructions • LEA : Load effective address ; LEA SI, [DI+BX+5H] • LDS, LSS, LES, LFS, LGS : Load full pointer (offset: SBA) into reg and seg reg • PUSH operation : ((SP)) ¬ (src) (SP) ¬ (SP)-2 flags affected: none • POP • PUSHA, POPA (all general registers onto/from stack) • PUSHF, POPF • Arithmetic Instructions • ADD, ADC, INC, AAA, DAA • SUB, SBB, DEC, NEG, AAS, DAS • MUL, IMUL, AAM, DIV, IDIV, AAD, CBW, CWD • AAA : ASCII adjust for addition; flags affected: AF, CF, OF, SF, ZF, PF undefined • operation: ALcarry ¬ (AL) >0F9H; if ((AL)&0FH) >9 or (AF) = 1 then (AL)¬((AL)+6)&0FH; (AH)¬ (AH)+1+ALcarry; (AF) ¬ 1; (CF) ¬1; else AF¬ 0; CF¬ 0; (AL) ¬(AL)&0FH ;

  10. Arithmetic Instructions • Example : AL : 32H ASCII code for number 2; BL: 34H ASCII code for 4 ADD AL,BL ---- AL :66H AAA ----- AL : 6H • DAA (Decimal adjust for addition: two packed decimal) • operation: if ((AL)&0FH)>9 or (AF)=1 then (AL) ¬(AL)+6, (AF) ¬ 1 if ((AL)&0F0H) >90H or (CF) =1 then (AL) ¬ (AL)+60H, (CF) ¬ 1

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