Low-Power Multipliers with Data Wordlength Reduction

1. Low-Power Multipliers withData Wordlength Reduction Kyungtae Han (khan@mail.utexas.edu) Brian L. Evans (bevans@ece.utexas.edu) Earl E. Swartzlander, Jr. (eswartzla@aol.com) Dept. of Electrical and Computer EngineeringThe University of Texas at AustinAustin, TX 78712 USA Asilomar Conference on Signals, Systems & Computers November 2nd, 2005

2. Outline • Introduction • Wordlength reduction • Power consumption • Analysis in switching expectation • FPGA dynamic power estimation • Conclusion

3. Introduction • Minimize power dissipation due to limited battery power and cooling system • Multipliers often a major source of power consumption in typical DSP applications • Multi-precision multipliers can select smaller multipliers (8, 16 or 24 bits) to reduce power consumption • Wordlength reduction to select any word size[Han, Evans, and Swartzlander 2004]

4. Wordlength Reduction in Multiplication Sign bit • Input data wordlength reduction • Smaller bits enough to represent, e.g. π x π ≈ 9 • Truncation • Signed right shift • Move toward the least significant bit (LSB) • Signed bit extended for arithmetic right shift

5. Power Reduction via Wordlength Reduction • Power dissipation • Switching power consumption • Static power consumption • Switching power consumption • Switching activity parameter, α • Reduce α by wordlength reduction What is relationship between wordlength and switching parameter, α, in power consumption?

6. Switching Activity in Multipliers • Logic delay and propagation cause glitches • Proposed analytical method • Hard to estimate glitches in closed form • Analyze switching activity w/r to input data wordlength • Does not consider multiplier architecture • Simulation method • Count all switching activities(transition counts in logic) • Power estimation (Xilinx XPower) • Considers multiplier architecture

7. Analytical Method • Consider stream of data for one of the multiplicands • Compare two adjacent numbers in stream after reduction • Expectation of bitswitching, x, withprobability Px • L-bit input data • Truncate input datato M bits (N bits areremoved) • N-bit signed rightshift in L-bit input(Y is sign bit) L bits M bits N bits S … … S … … S S … S S …

8. Analytical Method X has binomial distribution AlwaysL/2 (independent on M and N)

9. Analytical Method Wordlength (L) = 16

10. Wallace vs. Booth Multipliers Symmetric Asymmetric (one operand recoded) Tree dot diagram in 4-bit Wallace multiplier Radix-4 multiplier based on Booth’s recoding (Χ● a = P)

11. Dynamic Power Consumption for Wallace Multiplier (1MHz) Reduction (56%) Swapping (recode,nonrecode) 16-bit x 16-bit multiplier (Simulated on XC3S200-5FT256 FPGA)

12. Dynamic Power Consumption for Radix-4 Modified Booth Multiplier (1MHz) Sensitive (13%) Reduction (31%) Swapping (recode,nonrecode) 16-bit x 16-bit multiplier (Simulated on XC3S200-5FT256 FPGA)

13. Conclusion • Truncation to 8 bits reduces est. power consumption by 56% in Wallace and 31% in Booth 16-bit multipliers • Signed right shift exhibits no est. power reduction in Wallace multiplier (for any shift) and 25% reduction in Booth multipliers (for 8-bit shift) • Power consumption in tree-based multiplier • Highly depends on input data • Simulation of all switching activity matches analysis of switching activity in reduced multiplicands in Wallace mult. • Operand swapping can reduce power consumption • In Booth multiplier, non-recoded operand 13% more sensitive in power consumption

14. Thank You!

15. Backup Slides

16. Dynamic Power Consumption • 16-bit x 16-bit multiplier (Simulated on XC3S200-5FT256 FPGA) 31% 56% Swapping Radix-4 modified Booth multiplier (1 MHz) Wallace multiplier (1 MHz)