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SPP/FIELDS Time Domain Sampler Preliminary Design Review

SPP/FIELDS Time Domain Sampler Preliminary Design Review. Keith Goetz University of Minnesota Goetz@umn.edu. Time Domain Sampler. Time Domain Sampler (TDS) is based on previous instruments Based most recently on STEREO instrument Gathers impulsive events – voltage as a function of time

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SPP/FIELDS Time Domain Sampler Preliminary Design Review

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  1. SPP/FIELDSTime Domain SamplerPreliminary Design Review Keith Goetz University of Minnesota Goetz@umn.edu

  2. Time Domain Sampler • Time Domain Sampler (TDS) is based on previous instruments • Based most recently on STEREO instrument • Gathers impulsive events – voltage as a function of time • Centered peaks • Simultaneous sampling on all channels • Fixed sampling rate – 1.92MSa/s which is ~160Mb/s 24x7 throughput • Programmable effective sampling rate • Programmable event duration • Events have peaks - triggered • After that, flight software scores event based on programmable criteria • Quality can be adjusted – up or down - after the fact • When telemetry is available (nominally to DCB), best event is sent • When memory is needed (for a new event), worst event is deleted • Event selection can be based on quality or not – honesty • Delivered bit-rate is highly programmable – nominally 10kb/s • Low rate stream gives peak activity as a function of time

  3. STEREO snapshot

  4. STEREO snapshots

  5. STEREO snapshot

  6. Dust

  7. Big Dust

  8. TDS Heritage • Time Domain Sampler (TDS) is based on STEREO instrument • Changes - Science • Plasma frequency up from 10’s to 100’s of kHz – shock time scales are faster • TDS samples at ~2MSa/s and ~1MHz Nyquist • Programmable down-sampling • Continuous sampling – reduced power supply load variations • Direct deposit – increases duty cycle – eliminates event length limit • Wave-particle correlation with SWEAP • Changes – FIELDS System-6 • Added DPU functionality to TDS – similar to STEREO implementation • Communicates directly to S/C in addition to DCB • Controls MAGi, LNPS2, AEB2 • Communicates with SWEAP

  9. Waveform and Particles CLK ~2MHz Samples Δt = 500ns V(t) Δt = 500ns count(t)

  10. Waves and Particles Samples Δt = 500ns t = 1,500ns t = 2,000ns t = 2,500ns t = 3,000ns t = 3,500ns t = 4,000ns t = 4,500ns t = 5,000ns V(t) Δt = 500ns V = 0mV V = -2mV V = -4mV V = +5mV V = -12mV V = -15mV V = -10mV V = -5mV count(t) n = 2 n = 4 n = 2 n = 2 n = 7 n = 3 n = 5

  11. TDS Requirements • TDS-01Mission Length • TDS Components must be selected to withstand the environment of SPP for the duration of the mission. • TDS-02Spacecraft Interface Compliance (General) • TDS shall implement the spacecraft interface protocol… • TDS-03Timing from S/C • TDS shall provide latching facility upon detection of the "Virtual 1PPS" S/C timing signal… • TDS-04 • Timing from DCBTDS shall provide an electrical interface to the Data Control Board capable of…

  12. SWEAP Requirements • TDS-05 SWEAP Interface - CDI • TDS shall provide an electrical interface to the SWEAP instrument capable of sending CDI commands, receiving CDI messages: • [a] sending Command/Data Interface (CDI) messages to SWEAP; • [b] receiving SWEAP status and burst information from SWEAP; • [c] sending TDS time-keeping information; • [d] sending TDS clock synchronization. • TDS-06 SWEAP Interface – Particles • TDS shall provide an electrical interface to the SWEAP instrument capable of: • [a] receiving particle count information from SWEAP • [b] receiving particle synchronization and state information from SWEAP

  13. MAG Requirements • TDS-07 MAG Interface – CDI • TDS shall provide an electrical interface to the MAG Electronics capable of: • [a] setting control registers • [b] receiving MAG Science and Engineering data • [c] provide MAG AC heater synchronization

  14. AEB Requirements • TDS-08 Antenna Electronics Board Interface (AEB) • TDS shall provide an electrical interface to the Antenna Electronics Board capable of: • [a] setting Biasing D/A converters and relays • [b] reading back the biasing voltages • [c] provide DC-DC converter synchronization

  15. LNPS Requirements • TDS-09Low Noise Power Supply Interface (LNPS) • TDS shall provide an electrical interface to the Low Noise Power Supply capable of • [a] setting control registers for Power Control and Housekeeping Channel • [b] receiving an analog housekeeping signal • [c] provide DC-DC synchronization

  16. TDS Requirements • TDS-10 Time Domain Sampler Control • TDS shall provide electrical interfaces to the Time Domain Sampler data acquisition system capable of: • [a] setting TDS instrument modes • [b] receiving TDS instrument data • TDS-11 TDS Memory Management • TDS shall include memory such that: • [a] is capable of storing ~20 TDS snapshot events • [b] allows best available event to be sent to telemetry • TDS-12 TDS Instrument Calibration • TDS analog science and analog housekeeping conversion coefficients are determined and provided prior to S/C Integration to include gain, phase and timing

  17. Science Requirements • TDS-13 E Signals • TDS shall provide an electrical interface capable of: • [a] signal processing and measurement of the low frequency component of E-Field signals • TDS-14 E Signals • TDS shall provide an electrical interface capable of: • [a] signal processing and measurement of the AC or plasma frequency (ranging to ~1MHz) component of E-Field signals." • TDS-15 B Signals • TDS shall provide an electrical interface capable of: • [a] signal processing and measurement of the AC or plasma frequency (ranging to ~1MHz) component of B-Field signals (single axis)." • TDS-16 Instrument Calibration • TDS shall provide calibration parameters and algorithms so as to allow conversion from telemetry units to physical units (gain and offset per channel) prior to S/C Integration.

  18. TDS Block Diagram

  19. New - TDS FPGA Block

  20. FIELDS block diagram

  21. TDS BB2

  22. TDS – Single Board Data Acquisition System • Centers on RTAX4000 FPGA daughter board • Holds all logic, interfaces and LEON 3 processor instantiation • TDS event data gathered by 16-bit ADCs at ~2MSa/s • Multiplexed 16-bit data bus • Simultaneous acquisition of SWEAP particle counts • TDS event data stored directly into dedicated event memory • 16MB event SRAM – 8 parts – 512k by 32bits • Circular buffers • Processor support • 8-bit data bus • Local SRAM w/ ECC • Local boot PROM (some in FPGA?) • Local program EEPROM • S/C serial interfaces • CDI interfaces to DCB, MAG, SWEAP • Device interfaces – AEB, LNPS • Mezzanine interface • Diagnostic UARTs

  23. Configuration in Flight

  24. Test Configuration at UMN

  25. Resources • TDS mass CBE is 435g (not counting structure) • TDS power CBE is 2.17W secondary • TDS bit-rate to DCB (flash) is ~10,000 b/s

  26. Issues • TDS design is well advanced • Based on earlier STEREO implementation • More than usual at this point (PDR) • Selected ADC is great – but plastic • A cousin was used on STEREO • Putative parts have been obtained (x100) • Lead has been added • DPA has been completed (x5) well • Radiation and beam testing next • Up-screening after that • Backup solutions could be painful in performance and power • Astrium/ESA testing suggests we’ll be ok (only SEU/SEFI sensitive) • Overall power • We’re only now getting to good power estimates • LVDS protection solution is still open for S/C communications

  27. Next • Continue development work with BB2 • FPGA • FSW • Spacecraft Emulator • FIGs for DCB, MAG and SWEAP • Ground software • Modify existing schematic for ETU • Layout ETU

  28. SPP/FIELDSTime Domain Sampler FPGAPreliminary Design Review Keith Goetz University of Minnesota Goetz@umn.edu

  29. TDS FPGA • TDS is based on STEREO design • 3 STEREO FPGAs and 1 VLSI µP move into one FPGA for SPP • TDS is a combination of analog electronics, digital electronics, VHDL firmware and flight software • Added System-6 pieces fit in well • Low impact • TDS FPGA is central • RTAX4000 is the FPGA of choice • RTAX4000SL-1 CCGA-1272 • Maybe more than we need in gates but has lots of useable pins • CQ352 does not have enough user pins • FIELDS FPGA daughter board makes this a common part/design solution • Developed at UCB • Used in DCB, TDS and DFB • Risk reducer

  30. TDS FPGA Block

  31. TDS Data Acquisition/Control • Gather time series data • Access ADCs • Front end processing • Accumulate SWEAP counts and sync • Down sampling e-time series • Send buffered data stream to TDS memory controller • Never skipping a beat • Generate sampling clock • Select muxes

  32. TDS statistics Peaks and maxes Triggering Langmuir wave statistics Dust analysis High heritage

  33. TDS Memory Control • Accept data steam • Accept triggers • Control circular buffers • Large dedicated 32-bit memory path • Large dedicated event memory (16MB) • Interleave memory access from CPU

  34. TDS FFT Controller • Optional • Allows frequency analysis • Redundancy • Enhances dynamic range of new all-digital TNR • Large signal spectra • Could be done in hardware or software

  35. HK ADC Controller • New • Allow FSW access to external ADC/MUX • Analog HK • Analog Science

  36. S/C TM/TC Interface • New • UARTS to/from S/C • A/B • S/C Time, Status and Sharing • S/C commands • S/C telemetry • HK • MAGi • Provides one real-time clock • Common VHDL and FSW with DCB

  37. Clocks • Receive internal clock (from on-board oscillator) • Receive external clock (from DCB) • Fail-over and back • Slave to DCB when possible • Generate clocks for internal/external use • MAGi CDI (4.8MHZ) and heater (300kHz) • SWEAP CDI (4.8MHz) and high-rate clock (19.2MHz) • AEB2 conversion clock (300kHz) • LNPS2 conversion clock (600kHz) • ADC clocking • Maintain real-time clock from S/C • Maintain real-time clock from DCB

  38. Watchdog • Handles resets • Internal watchdog timer • Touched by FSW • If not touched delivers a reboot • Generally, the watchdog time is long • 220s in the past – shorter here

  39. DCB CDI • Standard CDI slave interface • 4.8MHz • Also includes high rate clock (38.4MHz) • DCB sends TDS time and commands • TDS sends DCB fully formed/compressed TDS CCSDS data packets • ~10kbps • Common VHDL and FSW with DCB

  40. MAG CDI New Standard CDI master interface 4.8MHz Also includes power supply chopping frequency (300kHz) TDS sends MAG time and commands MAG sends TDS data chunks – one per cycle Common VHDL and FSW with DCB

  41. SWEAP CDI • New • Standard CDI master interface • LVDS • 4.8MHz • Also includes high rate clock (19.2MHz) • TDS sends SWEAP time and commands • CBS • MAG vector • Once per cycle • SWEAP sends contributions to CBS

  42. AEB Interface • New • Parallel and serial interface lines • Controls Antenna Electronics Board parameters • Current and voltage biasing • Retrieves AEB HK • Controlling AEB MUX • Also includes power supply chopping frequency (300kHz) • Common VHDL and FSW with DCB

  43. LNPS Interface • New • Parallel interface lines • Controls MAG power • Retrieves LNPS2 HK • Controlling LNPS MUX • Also includes power supply chopping frequency (600kHz) • Common VHDL and FSW with DCB

  44. Test UARTS • Console • OOB commanding • Log • OOB event stream • GSE • OOB binary/packet data stream • Debug • Line drivers on GSE (mezz board)

  45. Test points • Board serial number • Blinking light • Software controlled • Test input ports • Test output ports • I/O to EM connector to allow timing/triggering tests

  46. Processor • LEON 3 IP • Free – open source • SPARC V8 • LEON 3 FT planned for flight • STEREO used an earlier version – SPARC V7 • IP • Gaisler GRLIB • LEON • AHB/APB infrastructure • GDB • GRMON • UARTs

  47. Processor Support • Interrupts • DMA Handler • Processor RAM • Internal and external • Processor ROM/PROM • Internal and external • Internal boot PROM? • Processor EEPROM

  48. Mezzanine Board • GSE only • RS-232 drivers • Reset button • Blinking light • Logic Analyzer interfaces • PROM/EPROM/EEPROM sockets • PROM emulator interface

  49. RTAX4000 Planned Resource Useage

  50. Peer Review Actions

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