Deployable IV&V Methods for FPGA Applications

1. Research and Development of Deployable IV&V Methods for FPGA ApplicationsNorthrop Grumman, KeyLogic Systems,Mountain State Information Systems, Inc., The University of Montana and West Virginia University July 20, 2006 SAS_06_FPGA_NGIT

2. FPGA Overview • FPGAs in the 1990s attained a threshold in performance and gate counts that permitted replacement of ASICs instead of just prototyping of the boards. • Engineers also realized that many common functions handled by micro-processors could be transferred to FPGAs, relieving processors of some duties and matching or exceeding performance and improving reliability. Micro-Processor Executed Functions ASICs FPGA Supporting Circuitry SAS_06_FPGA_NGIT

3. FPGA Overview • The first FPGA in 1985 (Xilinx) had ~1,000 gates. Gate counts now exceed 10 Million - a 10,000 fold increase while gate sizes and power consumption have fallen. • Hardware Description Languages (HDL), first VHDL and later Verilog were developed to describe, document and simulate VHSIC and later evolved into a means to synthesize FPGAs. • Initial FPGA designs could be accomplished with minimal attention to development lifecycle and instead retained “design & test” engineering practices. • Increased gates and complexity lead to difficulties in implementation, to failures, lessons-learned and is now leading to adoption of more formal development practices. • Some Common Failures in real FPGA development lifecycles are*: • No Specifications or the Specifications were not followed • Features added or deleted during development and not documented • No Stable Specification creating delays to Project (belated HW delivery to I&T) • Drifting software or system requirements impacted FPGA development • Reliance on logic simulators with insufficient time for V&V * A summary of development failures from presentation "Logic Design Pathology and Space Flight Electronics", R.Katz, et al. SAS_06_FPGA_NGIT

4. FPGA Overview • Creation of formal development practices and a lifecycle for FPGAs are still underway. Engineers realize that a software development lifecycle is applicable to FPGA development. Concept Requirements Design Implementation Test • FPGA design practices will continue to closely mirror software development but there are differences. • With FPGA engineering practices being formalized and with added complexity and impact on spacecraft system designs, the V&V of the FPGAs will become the responsibility of specialists. SAS_06_FPGA_NGIT

5. FPGAs & IV&V • As a comparison, software designs have become more complex and the importance of V&V is taking on a greater role and greater percentage of project resources. • Independent verification and validation has provided added assurance directly by identification of issues and indirectly by supporting adoption of formal methods. • FPGA development is following a similar trend toward formalized methods. This NASA IV&V supported project will develop IV&V methods and assess their feasibility. The questions – Is FPGA IV&V feasible, practical and effective, will be answered. • Could NASA IV&V analysts competently execute FPGA IV&V? NASA IV&V analysts have a wide range of expertise from software development, spacecraft design to electrical and aerospace engineering. With the commencement of FPGA IV&V, NASA IV&V will have analysts amongst their ranks qualified to undertake the tasks of FPGA verification and validation. SAS_06_FPGA_NGIT

6. Deployable IV&V Methods for FPGAs This initiative will involve 5 steps towards development of a deployable FPGA IV&V method 1. Surveying and cataloging existing FPGA applications 2. Concept/Requirements Phase: • Methods for Concept/Requirements analysis • Identify potential methods for full-lifecycle analysis 3. Design/Implementation Phase: • Dynamic analysis including functional and timing simulations at the unit level • Envisioned work instructions build on successful past analysis methods 4. Test Phase: • Define the types of design and implementation validation that can be practically accomplished via subsystem testing 5. Project transference: Continue with pilot and other projects SAS_06_FPGA_NGIT

7. Deployable IV&V Methods for FPGAs • Surveying and cataloging existing FPGA Applications • We will answer the question, how are FPGAs being utilized in aerospace applications? • A survey will be undertaken to identify the types and breadth of functions that FPGAs are taking. • The survey is expected to locate FPGA designs that can be acquired and used as test cases for this project. • Cataloging these applications will include an assessment of their design complexity. • Teams will be able to prioritize FPGA by their importance to overall system design. • Knowledge of complexities will permit IV&V teams to estimate resource requirements SAS_06_FPGA_NGIT

8. Deployable IV&V Methods for FPGAs • Concept/Requirements Phase • The project will decompose the content of FPGA concept and requirement documents. • Understanding the common aspects of FPGA design documents will permit creation of a methodology and to an IV&V checklist for the content of these documents. • This Project will define how to complete the IV&V tasks as defined in IEEE 1012 and NASA IV&V SLP 09-1 for FPGA designs. • As with software development, FPGA IV&V will look for completeness, consistency and accuracy. • How will we verify requirements flowdown for FPGA design? • How will interface between FPGAs and the subsystem in which it is embedded be verified?

9. Deployable IV&V Methods for FPGAs • Concept/Requirements Phase (continued) • Past NASA IV&V FPGA analysis included: • Verifying architectural diagrams against requirements & assertions. • Applying IEEE/ISA standards for HDL code (IEEE 1076 Standard VHDL) and verifying that engineers adhered to these standards • Verification of State Diagrams SAS_06_FPGA_NGIT

10. Deployable IV&V Methods for FPGAs • Design/Implementation Phase • Design Analysis can include validation of state diagrams • Documented diagrams can be analyzed. • Analyzer generated stated diagrams can validate design • Functional Simulations will provide initial validation of timing requirements and input and output signals. • Timing Simulations are required to validate FPGAs, i.e. Very High Speed Integrated Circuits (VHSIC). • Timing simulations are a challenge to the limited resources of the IV&V effort. Concise methods will be necessary to lead to efficient setup and execution of these simulations. SAS_06_FPGA_NGIT

11. Deployable IV&V Methods for FPGAs • Design/Implementation Phase (continued) • Past NASA IV&V FPGA analysis included: • Manual Walk-Throughs of the VHDL • Static analysis of the VHDL by the Active-HDL debugger • Functional Simulations that verified or found issues with state diagrams • Timing simulations • Trade study of FPGA developer tools SAS_06_FPGA_NGIT

12. Deployable IV&V Methods for FPGAs • Test Phase • Potential tools for validating FPGAs embedded in a subsystem include: • Simulink and Active-HDL or other applications that interface, but a trade study will be necessary to identify and assess all 3rd party utilities. • Evaluating the potential of simple test beds for validating FPGAs using off-the-shelf development boards. SAS_06_FPGA_NGIT

13. Deployable IV&V Methods for FPGAs • Project Transference • Steps 1-4 are scheduled within the first year of the project. Deliverables will justify the continuation into year two and feasibility of methods. • Final step is a pilot project that will assess and validate the feasibility of FPGA IV&V during the second year. SAS_06_FPGA_NGIT

14. Project Status • Commencement of project funding was June 2006 • A kick-off meeting with the NASA POC (K. Costello) was • completed. • Initial team meetings in July 2006 are being scheduled. • Project staffing will merge the expertise of a FPGA design • engineer, senior IV&V analysts and university researchers. • A Project Repository has been created (NG IMAP) and its • structure is under construction. Team members are collecting • reference documents for upload to the repository. SAS_06_FPGA_NGIT

15. Backup Slides SAS_06_FPGA_NGIT

16. Specifications

17. Active-HDL and FPGA Analysis