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REGISTER MANAGMENT TOOL

Middle presentation. REGISTER MANAGMENT TOOL. Preformed by: Liat Honig Nitzan Carmel Supervisor: Moshe Porian Date: 29/1/2012 winter semester 2011 Duration: One semester. Dress Specifications: Color: White Fabric: Lace Length: Long. Motivation:.

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REGISTER MANAGMENT TOOL

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  1. Middle presentation REGISTER MANAGMENT TOOL Preformed by: Liat Honig Nitzan Carmel Supervisor: Moshe Porian Date: 29/1/2012 winter semester 2011 Duration: One semester

  2. Dress Specifications: • Color: White • Fabric: Lace • Length: Long Motivation: Different designer - Different dress!

  3. Background Different teams use the register HSID But each team creates their own registers code… WHY?!?

  4. The Solution – a Register Management Tool Automatically generates registers according to the required specification. Enables REUSE Saves money and resources Creates unity in the registers VHD files

  5. The Solution – a Register Management Tool Manages the registers through the entire project Alarms in case of incorrect input Creates documentation for the components created Leads to an organized –HSID

  6. Project Specifications GUI demo • 1. Writing a GUI interface through which the user will determine a variety of attributes.

  7. Project Specifications GUI demo • 1. Writing a GUI interface through which the user will determine a variety of attributes. • 2. Interactivity - The tool will provide feedbackfor user errors • end will provide a summary output.

  8. Project Specifications GUI demo • 1. Writing a GUI interface through which the user will determine a variety of attributes. • 2. Interactivity - The tool will provide feedbackfor user errors • end will provide a summary output. Simulation Environment 3 • 3. VHDL: VHD files Local Bus Master 2 1

  9. Project Specifications GUI demo • 1. Writing a GUI interface through which the user will determine a variety of attributes. • 2. Interactivity - The tool will provide feedbackfor user errors • end will provide a summary output. Simulation Environment 3 • 3. VHDL: VHD files Local Bus Master 2 1 • 4. No special license will be needed to operate the tool, an EXE file will be given to the user.

  10. General Description Register Register Register Block Block Local Bus Register access Chip data I/O Block

  11. Block A Wishbone - open source protocol clk_i cyc_i stb_i adr_i BlockB dat_i we_i Wishbone Master dat_o ack_o Stall_o Block C

  12. Block A reset clk Top Architecture Block_A_reg_top Function_1 Reg_status_1 Function_2 Reg_enable_2 Wishbone Master Function_3 func_err_3

  13. Block_A_reg_top Reg Block Architecture Inputs from block Functional Block Reg1 WB Slave Outputs to block WB Master Reg2 Priority Encoder Reg3 4 reg_chosen Reg4 Data from chosen register

  14. clk_i Wishbone Slave Component WB Slave wbs_cyc_i wr_en wbs_stb_i wbs_we_i rd_en addr wbs_adr_i wbs_dat_i din wbs_dat_o dout wbs_ack_o din_ack wbs_stall_o dout_valid

  15. Idle wr_en=‘0’ rd_en=‘0’ (wbs_cyc_i )●(wbs_stb_i) Wishbone Slave Component (wbs_cyc_i )●(wbs_stb_i) Active Cycle wbs_stall_o=‘1’ Read Cycle rd_en=‘1’ Write Cycle wr_en=‘1’ wbs_we_i wbs_we_i dout_valid din_ack Cycle Finished wbs_ack_o=‘1’ wbs_cyc_i

  16. clk reset gen_reg Component gen_reg addr wr_en reg_in_b rd_en din dout din_ack dout_valid reg_chosen

  17. gen_reg Component Idle reg_chosen=‘0’ din_ack=‘0’ dout_valid=‘0’ addr==reg addr addr==reg addr addr==reg addr addr==reg addr The Register is chosen reg_chosen=‘1’ Write action Read action rd_en wr_en Register type is R/RW/COR/CONST Register type is R/COR/CONST Register type is W/RW Register type is W Valid Read Action dout_valid=‘1’ Invalid write Action din_ack=‘0’ Valid Write Action din_ack=‘1’ Invalid Read Action dout_valid=‘0’

  18. Register Types Read Write W/R Clear on Read (COR) Constant register Reg Block Functional Block Wishbone Master

  19. Register Types Read Write W/R Clear on Read (COR) Constant register Reg Block Functional Block Wishbone Master

  20. Register Types Read Write W/R Clear on Read (COR) Constant register Reg Block Functional Block Wishbone Master

  21. Register Types Read Write W/R Clear on Read (COR) Constant register “0000” Reg Block Functional Block Wishbone Master “0000”

  22. Register Types Read Write W/R Clear on Read (COR) Constant register “0100” Reg Block Functional Block Wishbone Master “0100”

  23. Register Types Read Write W/R Clear on Read (COR) Constant register “0101” Reg Block Functional Block Wishbone Master “0001”

  24. Register Types Read Write W/R Clear on Read (COR) Constant register “0101” rd_en = ‘1’ Reg Block Functional Block Wishbone Master “0000”

  25. Register Types Read Write W/R Clear on Read (COR) Constant register “0000” Reg Block Functional Block Wishbone Master “0000” “1010”

  26. Register Types Read Write W/R Clear on Read (COR) Constant register Reg Block Functional Block Wishbone Master

  27. Generic Implementation

  28. Generic Implementation

  29. Generic Implementation

  30. Simulation

  31. “00000000” COR register simulation “00000000” Functional Block addr = 0010 COR WB Master WB slave . . . . Encoder 4 Reg_chosen addr = 1110 W/R

  32. “00010000” COR register simulation “00010000” Functional Block addr = 0010 COR WB Master WB slave . . . . Encoder 4 Reg_chosen addr = 1110 W/R

  33. “00010000” COR register simulation “00000000” Functional Block addr = 0010 COR adr_i = 0010 WB slave WB Master we_i =‘0’ . . . . Encoder 4 Reg_chosen addr = 1110 W/R

  34. dout =“00010000” dout_valid = ‘1’ din_ack = ‘0’ “00000000” COR register simulation “00000000” Functional Block addr = 0010 COR adr_i = 0010 WB slave WB Master we_i =‘0’ . . . . Encoder 4 Reg_chosen addr = 1110 W/R

  35. Data from block = 1 COR register waveform 0 rd_en =‘1’ Scenario: the block updates the data while the master reads

  36. COR register waveform 0 Dout_valid = ‘1’ dout = “1” Results: updated data is transferred to the WB master reg_data is cleared

  37. COR register waveform 0 Reg_data = “00000000” Results: updated data is transferred to the WB master reg_data is cleared

  38. W/R register simulation Functional Block addr = 0010 COR adr_i = 1110 WB slave WB Master we_i =‘1’ dat_i = “00001101” . . . . Encoder “00000000” “00001101” 4 Reg_chosen addr = 1110 W/R

  39. W/R register simulation Functional Block addr = 0010 COR adr_i = 1110 WB slave WB Master we_i =‘0’ . . . . Encoder “00001101” 4 Reg_chosen addr = 1110 W/R

  40. W/R register simulation Functional Block addr = 0010 COR adr_i = 1110 WB slave WB Master we_i =‘0’ . . . . Encoder dout =“00001101” dout_valid = ‘1’ din_ack = ‘0’ 4 Reg_chosen addr = 1110 W/R

  41. W/R register waveform din = 7 and then 8 wr_en = ‘1’ for 2 cycles Scenario: WB master writes to register

  42. W/R register waveform din_ack = ‘1’ for 2 cycles dout = 7 and then 8 Results: updated data from WB master is transferred to register din_ack rises, indicating dout is updated Register not influenced by data from block (reg_in_b)

  43. W/R register waveform addr = 10 Dout_valid = ‘1’ rd_en = ‘1’ Scenario: WB master tries to read from this register’s address (register address is 10) Result: dout_valid rises to ‘1’

  44. W/R register waveform addr = 15 Dout_valid = ‘0’ rd_en = ‘1’ Scenario: WB master tries to read from another register’s address (register address is 10) Result: dout_valid is ‘0’

  45. Project Steps • Determine the implementation platform of the user interface and data processing: Excel/MATLAB/C++/C#/JAVA . • 2. Full characterization of the tool capabilities. • 3. Learning the working environment (Wishbone protocol, advanced • VHDL coding , MODELSIM simulation environment). • VHDL generic design and simulation. • Implementing the GUI and automatic VHDL generation. • 6. Final MODELSIM and MATLAB Simulations. In process

  46. Schedule

  47. The End

  48. GUI Demonstration Back

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