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“TDAQ for 2012 runs ”

“TDAQ for 2012 runs ”. Gianluca Lamanna (CERN) Annual review meeting 02.04.2012. Dry Run & Technical run. The October Technical Run is a good opportunity to test the TDAQ structure and to readout data for detector calibration. The TDAQ is a relatively complex system .

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“TDAQ for 2012 runs ”

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  1. “TDAQ for 2012 runs” Gianluca Lamanna (CERN) Annual review meeting 02.04.2012

  2. Dry Run & Technical run • The October Technical Run is a good opportunity to test the TDAQ structure and to readout data for detector calibration. • The TDAQ is a relatively complex system. • To better take advantage of the beam time available, it’s mandatory to test all electronics equipments that will be used in the technical run  Dry Run will start July 15 (for 1 month) • Some amendment to this law is possible in case of no interference with other systems.

  3. TDAQ concepts Data Trigger primitives TTC L1 requests L1/L2 PCFARM Synchronous detector • For most of the detectors the readout and the definition of trigger primitives is done with the same FPGAs. • The primitives trigger transmission is asynchronous while trigger decision transmission is synchronous. 10 MHz TEL62 1 MHz L0TP (1 ms max latency) 10 kHz detector TEL62 TEL62 Asynchronous detector 100 kHz

  4. TDAQ for 2012 • PCFarm • Network • Online software • Run Control • L0TP (TALK) • LTU & TTCex • TTC Front end electronics Readout & Trigger Data acquisition • LAV FEE • CEDAR board • CHANTI board • STRAW readout • CFD board • TDCB • TEL62 • SLM

  5. Overview of 2012 runs TDAQ hardware

  6. LAV FEE board • ToT(Time Over Threshold) with large dynamic range • Double threshold • Redundant front end • Slewing correction • Control PC, pulser and signal sum • 9U board with mezzanines • 32 input, 64 output • 31 boards in production • Ready and tested for the end of May

  7. CEDAR board • “Amplificator-free” board to house NINO chips. • The differential signals are obtained using the last dinode. • 128+5% special PM sockets in production (end of may). • The final board design is started: final tested board ready for the middle of July. • Since the PMs will be installed after the Dry Run, a procedure to pulse the NINOs from the readout is foreseen.

  8. CHANTI board • CHANTI board: • Provides Vbias for SiPM • Fast amplification • Reads currents (nA) for monitoring • Reads temperatures probes • 4 channels prototype has been built: • Standalone lab test passed • Test with the CHANTI prototype are ongoing • The final board will be ready at the end of June CHANTI board 32 Ch. LAV FEE board 32 Ch CHANTI

  9. STRAW readout Cover board Cover board Cover board Cover board Cover board Cover board Cover board Cover board Cover board Cover board SRB SRB SRB TEL62 daughter board • Cover board and SRB(Straw Readout Board) prototypes are ready: • Cover board final production in June • SRB final prototype will be ready in June with a simplified version of the firmware. • TEL62 daughter board prototype ready in October • In the Technical Run the readout will be done using VME (fall back solution), in case the daughter board will not be ready. STRAW (1 view) VME … 30 boards per view…

  10. CFD • The CFD(Constant Fraction Discriminator) coming from the NA48 AKL readout system will be reused for the MUV3 frontend this year • We need 19 boards: • We have already 18 working boards (additional tests needed) • We will produce few additional boards (3 or 4), probably ready in July • A level adaptor board (TRAM-TRAnslator for Muon veto) will be ready in June EB24 Flat cable TDCB cable RG58 Lemo ECL->LVDS (TRAM board) Patch panel MUV3 CFD TDCB/TEL62

  11. TEL62 • The TEL62 is a main board to digitize (using daughter boards), buffer data and to build trigger primitives. • It’s an evolution of the LHCbTELL1 board. • 13 boards in production: will be ready at the end of April. • Special crates ordered will arrive after Easter.

  12. TEL62 Firmware • A prototype firmware for the readout will be ready in May. • The firmware to produce trigger primitives depends on the manpower (see later).

  13. TDCB • The TDCB board is a TEL62 mezzanine. • 4 HPTDC for a total of 128 channels per board (512 per TEL62). • 12 boards already distributed to sub-detectors groups. • 12 additional boards will be ready at the end of April.

  14. SLM & TALK board • 40% of the channels are already equipped with new Fastbus power supply. • The CREAM(Calorimeter REAdout Module) systemwill be ready in 2013. • For the 2012 runs we will use the old readout (CPD (Calorimeter Pipeline Digitizer)) with the SLM(Smart Link Modules) to bring data inside readout PCs. • The trigger distribution will be done using the TALK(Trigger Adaptor for LKr) board. To CPD TAXI TEL62 PP TTC TALK FPGA PP SL PP PP to R/O PC

  15. TALK board as L0TP • The TALK board will be used during the 2012 runs as L0TP(L0 Trigger Processor) • FPGA, 5 Ethernet connectors, input/output LEMOs, RJ11 for choke/error, connector for the LTU(Local Trigger Unit), connection with the TEL62. • The board is ready and tested. • The firmware is almost ready.

  16. Triggering with TALK board • Two ways: • With LEMO. • Using the primitives produced inside the TEL62. • The use of the asynchronous primitives is the baseline solution. This depends on the specific firmware inside the TEL62. • The fall back solution will be done using the signals coming directly from the FEE boards. CHOD TALK eth TALK lemo TEL62 LAV

  17. Trigger partition: LTU & TTCex • The L0TP will communicate trigger decision through TTC system. • The trigger partition for each detector is composed by LTU+TTCex and optical splitters. • The LTU+TTCex for 2012 runs has been already produced and distributed to the sub-detectors groups. • The firmware and the control softwareare complete.

  18. Clock & Trigger distribution • The fibers for clock & trigger distribution will be installed this week. • The copper cables for choke/error will be installed after the fibers. • A board to make the control signals “local OR” (CHEF – CHoke and Error Fan in) has been designed and will be ready in June.

  19. PCFarm & Network PCFarm HP8219 HP2910 • 7 x HP2910 already bought. • HP8212 ordered with 3 “8x10Gb/s” modules and 1 “24x1 Gb/s” module (middle of May). • Six 12 cores PCs foreseen for this year (to partially test the switches): • 2 already available. • 4 to be buy soon. • 10 Racks with cooling door ordered (end of April). HP2910 1 Gb/s copper 10 Gb/s fiber HP8212

  20. Readout software & Run Control • Readout software almost ready: prototype at the end of April. • Run Control program in preparation in collaboration with the EN/ICE group: base on PVSS, SMI++ and DIM.

  21. Summary • Most of the Hardware will be ready in June. • We will have readout firmware for TEL62 in May. We hope to have the firmware to test the asynchronous part of the TDAQ system (it depends on man power). • Network, trigger distribution and control lines infrastructure will be completed in April. • The PCFarm and the software will be tested in May.

  22. SPARES

  23. GPU • During the Dry Run/Technical run we have the unique possibility to test a real “demonstrator” parasitically connected to the TDAQ. • We are preparing a framework to run efficiently GPU algorithms. • For this year we will try to make the CHOD corrections in the GPU. • Some work is needed on the TEL62 firmware to send out reduced data for the GPU.

  24. TRAM board • TRAnslator for Muon veto • ECLTTLLVDS • Each board: 64 inputs on 4 cables, two TDCB standard cable in outputs • 9U TEL62 format (+5V, -5V, +3.3V from the connector) • The schematic has been prepared by Riccardo and my self • Mainz will take care to make the layout and to produce the board

  25. CHEF Board • CHoke and Error Fan in • 8 inputs, 3 outputs (one common output, two 4 channels output) • VME 6U for LKr, 1U format (with external power supply) for other detectors • LAV (already in 2012), CEDAR, STRAW, RICH, MUV, LKr Patch panel CHEF crate

  26. CHOD FEE • CHOD is evaluating two possibilities for the readout: • Florence NINO board with attenuation • LAV FEE (baseline) • The advantage to use the NINO board is in the number of TDC channels (128 instead of 256) • An attenuation of ¼ isn’t enough to go in the linearity region of the NINO • A greater factor could affect the efficiency

  27. LKr Trigger distribution • The TALK board will be used for the LKr trigger distribution • The TAXI has been tested in the Lab, we need to test it in the real system TAXI receiver PECL clock

  28. TALK firmware

  29. Data pulser • Both in LAVFEE and in the CEDAR FEE it’s possible to generate pulses using the last pair in the TDC cable. • The TEL62 can trigger the pulser. • The signal TEL62TDCBFEE is sent for pre-decided timestamps; at the same time the L0TP will produce a trigger request. • For the LKr the same things can be done using one TALK board output. Cedar NINO Board Data Pulser TDCB TEL62 TTC Timestamp: 0xA0A0A0A0 Send calibration trigger request L0TP L0TP 1 ms t TEL62 Timestamp: 0xA0A0A0A0 Send pulser signal to FEE

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