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Exception Processing

Exception Processing. ECE511: Digital System & Microprocessor. What we are going to learn in this session:. What are exceptions. How M68k handles exceptions. M68k execution states and how they relate to exception handling. Introduction. Exceptions.

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Exception Processing

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  1. Exception Processing ECE511: Digital System & Microprocessor

  2. What we are going to learn in this session: • What are exceptions. • How M68k handles exceptions. • M68k execution states and how they relate to exception handling.

  3. Introduction

  4. Exceptions • Out-of-ordinary events that happen during M68k run-time. • Caused by: • Interrupt requests. • Errors during processing cycle. • Arithmetic operations that cannot be completed. • Illegal instructions.

  5. Exception Example (Divide by Zero) • MOVE.W #0,D0 • MOVE.L #500000, D1 • DIVU D0,D1 500,000 / 0 = ? * Divide by Zero Exception

  6. Exception Example: Address Error • Memory range = $000000 to $004000 • MOVE.B #$0A,$004500 $0000 $0001 $0002 … * Address Error Exception … $3FFE $3FFF $4000 $4500? (Address out of range)

  7. Exception Example: Address Error • MOVE.B #$A00A,$000001 Word transfer to odd address. $0000 $0001 $0002 … * Address Error Exception … $3FFE $3FFF $4000

  8. External Peripheral M68k T S I2 I1 I0 X N Z V C Exception Example: Interrupt Request M68k is executing instructions normally. 1 2 External peripheral has important task for M68k. 3 External peripheral asks for attention by outputting interrupt on IPL0, IPL1, IPL2. M68k compares interrupt level to SR. 4 M68k services/holds interrupt based on interrupt level 5

  9. S0 S2 S4 S6 S0 S2 S1 S3 S5 S7 S1 Exception Example: Spurious Interrupt CLK A1 – A23 AS LDS/UDS R/W DTACK DTACK never responds D0 – D15 FC0 – FC2

  10. Exceptions • Exceptions should be handled properly: • Can cause data loss. • System failure. • No prioritizing of tasks. • M68k handles exceptions using Exception Handling.

  11. M68k Execution States

  12. M68k Execution States • M68k always functions in either of the three states: • Normal. • Halted. • Exception.

  13. Normal State • M68k operating normally. • Executing in user mode (S=0). • Has a restricted instruction set: • Can’t execute privileged instructions. • Prevents from executing potentially destructive instructions. • Reserved for SV.

  14. Restricted Commands in Normal State • STOP • RESET • RTE • Any commands that modify the SR. • MOVE USP

  15. Exception State • Handles special events (exceptions), then returns to normal execution. • Can execute all instructions. • Always saves processor context before handling exception, restored when returned to normal execution. • Always executes in SV mode (S=1).

  16. The Status Register T S I2 I1 I0 X N Z V C Supervisor Mode, S = 1 (Exception State, Halted State) User Mode, S = 0 (Normal State)

  17. Halted State • M68k stops execution of all instructions. • Done by activating HALT line: • Stops execution after current instruction. • Waits until HALT is inactive. • Resumes normal execution.

  18. Halted State • Reason: • Catastrophic system failures (double bus faults, hardware failure). • User: intentionally activating the HALT line. • Purpose: • Protect data inside memory.

  19. How States are Changed S=1, Exceptions, Interrupt Double bus fault/User-initiated Normal Exception Halted S=0, RTE, Edit SR Reset Exception User-initiated

  20. Exception Handling

  21. Exception Handling • Series of steps performed to handle exceptions. • Ensures exceptions processed properly & resume normal execution. • Allows M68k to: • Save all processor status before exception. • Handle the exception. • Restore processor status when exception has been handled.

  22. What Happens During an Exception? • Contents of SR saved to memory. • S bit is set. • Exception vector is obtained. • Processor context (PC & SR) saved on software stack. • PC set to address of exception vector. • Execution resumes from new PC location. • Control and context restored & execution resumes from last address before exception.

  23. Exception Handler Operation Save D0-D7, A0-A7 Save PC and SR to stack. Handler Code TRAPV Read handler address from Vector Table. Reload D0-D7, A0-A7 Read original PC and SR from stack. RTE Next Instruction

  24. Exception Processing Steps

  25. Exception Processing Steps • Adjust SR. • Get Vector Number. • Save processor information. • Fetch new PC. • Restore context, resume last instruction in Normal mode.

  26. Step 1: Adjust SR • To enter SV state and prepare for exception processing: • Store SR internally. • Set S = 1 (SV Mode). • Set T = 0 (Disable Tracing). • If interrupt, update Interrupt Mask Bits.

  27. SR Bits Modified by Step 1 T S I2 I1 I0 X N Z V C T = 0 S = 1 Updated if: IREQ > ICURRENT

  28. Step 2: Get Vector Number • Determines what type of exception, and get location of its appropriate handler. • VN: 8-bit value indicating exception type. • Supplied by external device or M68k. • What kind of exception is happening. • Ranges from $00 (0) to $FF (255). • VN used to find Vector Address (VA).

  29. Vector Address (VA) • Special memory location that stores addresses of exception handlers. • VA obtained by multiplying VN with 4. • VN x 4 = VA. • VA contains a long-word value containing address of exception handler. • Contents insideVA loaded into PC, execution continued at this location.

  30. How Exception Handling Works VA = VN x 4 $3000 Exception handler code $3002 VN $3004 $0006 $0000 xxx $0018 RTE $0004 xxx $0008 $3000 VN $000C xxx $0010 xxx PC $3000 • VN given by external • circuit/M68k. Based on VN, • M68k knows what type • of exception has occurred. 3. M68k saves registers into stack, execution resumes at exception handler address. 2. VN x 4 = VA. Address of exception handler contained inside VA. M68k loads value into PC.

  31. VN VA = VN x 4 Assignment 0 0 = $0000 Reset: Initial SSP and PC 2 8 = $0008 Bus Error 3 12 = $000C Address Error 5 20 = $0014 Divide by Zero 8 32 = $0020 Privilege Violation 9 36 = $0024 Trace 24 96 = $0060 Spurious Interrupt 25-31 $0064 - $007C Interrupt Auto-vectors 32-47 $0080 – 00BC TRAP Instruction Vectors Vector Table (Antonakos, pg. 110)

  32. Step 3: Save Processor Information • Saves processor context into stack: • PC: next instruction after exception processing. • SR. • Bus cycle attempted, part of instruction (for bus error and address error). • SSP is used  already in SV mode.

  33. How Context Saved into Stack – Typical Exception New SSP location  Status Register PC (High Word) PC (Low Word) Old SSP location 

  34. How Context Saved into Stack • PC = $001111 • SR = $0115 • SSP = $002FFF $0115 New SSP location  $002FF8 SSP-6 $0000 SSP-4 $002FFB $1111 SSP-2 $002FFD … Old SSP location  SSP $002FFF

  35. Step 4: Fetch New PC • Loads PC from vector table in Step 2. • Processing resumes at exception handler. • Returned to normal processing using (Return to Exception) RTE.

  36. Exception Handler • Contains instructions on how to process the exception. • Located in SV memory space. • RTE at the end, resumes normal execution.

  37. Exception Handler Contents Save Registers Save Registers, PC into Stack Handler Code Code to handle exception Reload Registers Reload Registers from Stack RTE (Return to Exception) Reload PC from stack, execution resumes at next instruction after exception.

  38. Exception Example (Divide by Zero) • MOVE.W #0,D0 • MOVE.L #500000, D1 • DIVU D0,D1 • PC = $1040 • SR = 500,000 / 0 = ? * Divide by Zero Exception T S I I I X N Z V C 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 6

  39. Step 1: Adjust SR • Store SR internally. • Set S = 1 (SV Mode). • Set T = 0 (Disable Tracing). • If interrupt, update Interrupt Mask Bits.

  40. T S I I I X N Z V C 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 0 Step 1: Adjust SR T = 0 S = 1 Not interrupt = unchanged

  41. Step 2: Get Vector Number • Divide by zero exception VN is VN = 5 • VN x 4 used to find Vector Address (VA). VA = VN x 4 = 20 = $000014

  42. Vector Address (VA) • Special memory location that stores addresses of exception handlers. • VA obtained by multiplying VN with 4. • VN x 4 = VA. • VA contains a long-word value containing address of exception handler. • Contents insideVA loaded into PC, execution continued at this location.

  43. Vector Table Address Value $0000 $00400500 $0008 $00400600 $000C $00400700 $0014 $00400800 $0020 $00400900 $0024 $00400A00 $0060 $00400B00

  44. Step 3: Save Processor Information • Saves processor context into stack. • SSP is used  already in SV mode. $0016 (SR) New SSP  $3FFA PC = $001040 SSP/A7 = $004000 SR = $0016 $0000 (PC) $1040 (PC) Old SSP  $4000

  45. Address Value $0000 $00400500 $0008 $00400600 $000C $00400700 $0014 $00400800 $0020 $00400900 $0024 $00400A00 $0060 $00400B00 Step 4: Fetch New PC • Loads PC from vector table in Step 2. • Processing resumes at exception handler.  New PC = $00400800

  46. Exception Handler Contents $00400800 Save D0-D7, A0–A7 Save Registers into Stack Handler Code Code to handle exception Reload D0-D7, A0-A7 Reload Registers from Stack RTE (Return to Exception) Reload PC, SR from stack, execution resumes at next instruction after DIVU.

  47. Handling Multiple Exceptions

  48. Handling Multiple Exceptions • It is possible for another exception to happen when the current exception is being handled. • An bus error occurs when M68k is handling an interrupt. • A trace exception generated during a divide by zero exception.

  49. How does M68k handle multiple exceptions? • In M68k, each exception has priority level: • Reset exception has higher priority than Trace exception. • An interrupt exception is more important than a Divide-by-Zero exception. • When multiple exceptions happen, the more important one executed first.

  50. Group Exception Priority 0 Reset (Highest) (Lowest) Bus Error Address Error 1 Trace (Highest) (Lowest) Interrupt Illegal Privilege 2 TRAP All have same priority. TRAPV CHK Zero Divide Exception Grouping & Priority Importance

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