Elena Suvorova St. Petersburg State University of Aerospace Instrumentation

1. TOOLSET FOR TEST AND VERIFICATION OF IP-BLOCKS WITH SPACEWIRE INTERFACESession: SpaceWire Test and Verification Elena Suvorova St. Petersburg State University of Aerospace Instrumentation 67, Bolshaya Morskaya st. 190 000, St. Petersburg RUSSIA E-mail: suvorova@aanet.ru,

2. In this presentation we suggest : • Methods and toolset for IP-blocks and devices test and verification (RTL, post-synthesis and post-implementation netlists ) • SpaceWire BFM model as part of this toolset

3. BFM • Toolset for test and verification of RTL, post-synthesis and post-implementation models of devices includes different communication controllers is usually based on BFM. • The BFM (Base Formal Model) typically is used for testing and verification of interfaces that correspond to different standards. • (Other term BFM – Base Functional Model is typically system level model of a particular device or IP-block).

4. Requirements toBFM • BFM could be used for test and verification of interfaces includes different subsets of SpaceWire standard layers • Therefore BFM could have multilayer structure that corresponds to SpaceWire standard • BFM is system level model and typically written on SystemC (and interfaces of BFM layers typically not based on sc_signals, because simulation of model based on this interface type is very slow), but Layers of BFM could be connected to RTL models and netlists written on VHDL or Verilog. Also we suggest use wrappers to signal interface for every BFM layer • Imitation of all possible error situation for examination UUT behavior in these situations

5. BFM STRUCTURE Example of interface structure (logical ports): int send_Ccode(t_code Ccode_); bool ready_to_send_Ccode(); t_code receive_Ccode(); bool received_Ccode(); Example of wrapper to RTL or Netlist: Signal based interface Logical port

6. The problem of UUT configuration • We need to set UUT regime for test and verificationfor example: • link_disable, link_start, autostart values; • UUT tx speed value; • Routing table • We need to control : • state of UUT, • control codes and packets send by test shell when they received by UUT • Possibility of UUT to send control codes and packets correctly • The problems: • The IP-blocks and devices have different interfaces • The different address distribution in configuration address space for different types of IP-blocks and devices In this presentation we suggest possibledecision of different interfaces problem

7. Example of test shell for IP-block Typical SpW coder|decoder wrappersync memory wrapper Special wrapper written by UUT developer Write regime Read state of UUT General test structure: Set_regime_uut (regime); Set_regime_SpW_BFM (regime) Send_data_bfm(data1); Receive_data_uut(*data2); //comparison of results (data1 and data2) Send_data_uut(data1); Receive_data_bfm(data2); //comparison of results (data1 and data2) In this presentation we don’t consider details of xxx_uut functions. It depends on UUT address space and could include possible decision of address distribution in configuration address space difference problem

8. Test of devices with internal RISC core • The problem of synchronization between test program (in test shell) and device configuration (performed by software on internal RISC core) • The problem of analysis of UUT device current state Decision – using of special software on internal RISC core – this software read and implement commands from test shell

9. Example of test shell for device with SpW controllers and internal RISC core Special universal software (written on C) Read command, write data • command: • Read data • Write data • Nop (empty command) Write regime Read state of UUT

10. Test tools: • SpaceWire BFM • Test generators and controllers for all layers of BFM • Wrappers to signal interface for all layers of BFM • Wrappers to parallel synchronous memory interface, to serial memory interfaces (I2C, SPI, USB) • Memory model • Elementary switch model • Universal software for test UUT devices with internal RISC cores

11. Thank you!