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Tiger Quick Reference - Digital

Tiger Quick Reference - Digital. Enhanced signals diagrams and pin maps/layouts. This package is a compilation of detailed information on the Tiger Digital System for diagnosing faults. It contains overall and detailed digital diagrams, signal paths, cabling and pin maps.

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Tiger Quick Reference - Digital

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  1. Tiger Quick Reference - Digital Enhanced signals diagrams and pin maps/layouts 12/02/02

  2. This package is a compilation of detailed information on the Tiger Digital System for diagnosing faults. • It contains overall and detailed digital diagrams, signal paths, cabling and pin maps. • It is an addendum to the Tiger Signals Service Documentation CD. 12/02/02

  3. Table of Contents Page # • Overall Diagram 4 • Tester/Testhead Type Definitions 5 • TCIO and State Bus Path 9 • Clocks 10 • Matrix path 11 • Calibration path 22 • HSD Calibration 24 • Digital Power 42 • Board-installed Signal Flow 44 • TJA inputs from HSD 46 • Digital cable diagram 48 • Digital and AC signal card pin outs 50 • THADS Bus 93 12/02/02

  4. Overall Diagram QSB #1 949-873-xx Slot 49 PE32s 949-870-xx Slots 44-48, 50-53 QSB #4 949-873-xx Slot 58 PE32s 949-870-xx Slots 54-57, 59-62 Digital Backplane A 949-881-00 J1 J13 J4 J58 J54-J57 J59-J62 J49 J44-J48 J50-J53 J11 TJA TJA Caltree Caltree Caltree Sync In Caltree Caltree I/O Caltree I/O 800 MHz Clk HSD Sync Out TCIO/State Bus 100 MHz Clock 100 MHz Clock 807-430-00 807-430-00 Matrix, Cal, DGS Matrix, Cal, DGS TCIO/State Bus 807-425-00 807-426-00 807-427-00 807-429-00 Tester Computer BIF PCI Slot 3 807-433-00 807-436-00 CSB Board 949-920-60 CSB Slot 1 Splitter Board 949-866-00 CSB Slot 2 807-432-00 To Digital BP B J12 J2 807-434-00 807-437-00 807-436-00 To Digital BP B J30 and J39 CSB Backplane To TH Control Panel 807-429-00 To Dig BP A, J5 and J8 Digital BP B, J6 and J7 J2 J7 J8 J6 804-257-00 807-428-00 TCIO/State Bus ACISB-A 949-886-01 Slot 1 807-425-00 807-431-00 To QSB1, Dig BP A, J1 To PACS BP #1 Slot 8 807-425-00 To QSB2, Dig BP B, J2 807-425-00 To QSB3 Dig BP B, J3 Analog BP PPCLK100 807-425-00 To QSB4, Dig BP A, J4 J16, J17 J23 To DC Measurement System 807-442-00 100 MHz Clock 807-426-00 To QSB1, Dig BP A, J49 10/100 MHz Ref. Mod 807-426-00 To QSB2, Dig BP B, J39 To DIB Cable 807-444-00 807-426-00 To QSB3 Dig BP B, J30 From CSB BP, J6 807-425-00 J14 807-426-00 To QSB4, Dig BP A, J58 { 807-426-00 From CSB BP, J2 804-336-00 807-433-00 Sync In 807-427-00 Test Head Digital Backplane A (Quadrants 1 & 4) To QSB1, Dig BP A, J49 TJA 807-433-00 To QSB1, Dig BP A, J49 To SCS Slot 22 TMB #1 807-433-00 To QSB2, Dig BP B, J39 807-433-00 To QSB3 Dig BP B, J30 QSB #2 949-873-xx Slot 39 PE32s 949-870-xx Slots 35-38, 40-43 QSB #3 949-873-xx Slot 30 PE32s 949-870-xx Slots 25-29, 31-34 807-433-00 To QSB4, Dig BP A, J58 From Analog BP J16 and J17 807-442-00 Digital Backplane B 949-882-00 DC Measurement System J2 J12 J3 J30 J39 J35-J38 J40-J43 J25-J29 J31-J34 TJA Caltree Caltree Caltree Caltree TJA Caltree I/O Caltree I/O 100 MHz Clock TCIO/State Bus 807-430-00 807-430-00 100 MHz Clock TCIO/State Bus Matrix, Cal, DGS SUPPORT CABINET 807-425-00 { 807-426-00 807-433-00 807-429-00 807-436-00 807-432-00 To Digital BP A J11 807-436-00 To Digital BP A J49 and J58 807-429-00 12/02/02 From CSB BP, J8 807-425-00 { 807-426-00 From CSB BP, J2 807-433-00 Test Head Digital Backplane B (Quadrants 2 & 3)

  5. Tester/Testhead Type Definitions During Tiger System power up, the hardware is interrogated in order to determine the “type” of system. A hardware malfunction or cabling problem can cause the system type to be reported as something other than a TIGER. 12/02/02

  6. 804-258-00 804-257-00 807-428-00 10/100 MHz Reference 949-703-00 BIF 949-823-01 CSB 949-920-xx SPLITTER 949-866-00 J13 J3 J2 J2 J2 J7 J6 TIGER TEST SYSTEM Tester/Testhead Type Definitions: TESTER: 1. Power is off Tester Empty 2. AD802-02 UB Interface Present Tester A565 3. AD934 MFS HSD50 Tester A5zz 4. LA621 CSB HSD100 Tester Beta (CAT) 5. AD731 VB Cage Interface if present: Tester A500 if NOT present Tester A520 6. LA866 TIGER Splitter Tester TIGER 7. None of the above (2-6) Tester A510 TESTHEAD: 1. Power is off Testhead Empty 2. AD834 Data Buffer in slot 53 Testhead A500 3. AD667-01 Cal Strobe Buffer Testhead PATH II 4. AD834 Data Buffer in slot 13 Testhead ADV LINEAR 5. AD936 HSD50 Support Board Testhead ADV MIXSIG 6. LA873 QSB in slot 49 or LA886 ACISB in slot 1 Testhead TIGER 7. A510 or A520 - remaining unmapped Testhead A510 Messages 1.SYSTEMPOWER IS OFF or TERABUS NOT TERMINATED: If TBA Present: Check that the 5V on the AD701 is present. (The LED on the AD701 does not mean that the 5V is within spec.) Check the 800-321 & 804-256 Cables. Check the AD701 Terminator Board (879-701 804-256-00 800-321-00 DIGITAL I/F 879-802 Slot 1 UB TBA 949-824 J3 J4 Terminator Plug 807-358-00 J3 TERMINATOR 879-701-01 5V 2.SYSTEM Registers as A565 Reason: No Digital; “Sees” the AD802, but not the LA866 Splitter. TCIO cable 804-257 problem or the CSB (TCIO Bus A/B to CSB). Note: Check cable(s) and CSB; review the detailed system configuration and observe what hardware is not recognized. 3.SYSTEM Registers as EMPTY: (May show as a Simulator) TCIO Problem. Check both TCIO Cables - 807-257 & 807-258. Check the clock cable connecting the LA703 10/100 MHz Ref to the BIF. See diagram above. 12/02/02

  7. 804-256-00 800-321-00 J4 TBA 949-824-xx Terminator Plug 807-358-00 J3 TERMINATOR 879-701-00 5V Testhead Digital BP A J1 QSB #1 949-873-xx J49 804-258-00 804-257-00 807-428-00 807-425-00 10/100 MHz Reference 949-703-00 BIF 949-823-01 CSB 949-920-xx SPLITTER 949-866-00 J13 J3 J2 J2 J2 J7 J6 TH I/F 879-726-00 Slot 3 SCS Testhead Analog BP J11 804-256-00 800-321-00 804-305-00 ACISB-B 949-886-00 J4 J4 TBA 949-824-xx Terminator Plug 807-358-00 J3 J3 DIGITAL I/F 879-802-00 Slot 1 UB 5V TERMINATOR 879-701-00 4. System is: Failing raw DC power supply and temperature checks; Unable to map the AC channel cards; Mapped as empty. The TERABUS is cabled incorrectly or the cable is faulty. Verify the connections of the TERABUS cable and that there is an 807-358-00 terminator on J3 of the TBA. Check the 804-256-00 cable and the 800-321-03 cable. 5. TESTHEAD IS EMPTY Neither the LA873 QSB in slot 49 or the LA886 ACISB in slot 1 of the testhead can be found. Check the paths below for the signal path to readback the QSB and ACISB. Note: Only one of the paths below is needed to recognize the testhead as a “TIGER”. 12/02/02 5V

  8. PACS Card Cage PSB 949-671 J1 804-258-00 804-257-00 807-428-00 10/100 MHz Reference 949-703 SPLITTER 949-866 BIF 949-823 CSB 949-920 J3 J2 J2 J2 J13 J6 J7 807-425-00 PE32 or DPE32 805-870 805-902 Testhead Digital BP A QSB #1 949-873 J49 807-430-00 J1 879-289 Data Station TATS Card Cage J1 800-321-01 879-791 SBE SCS Card Cage 879-289 Data Station J4 J3 J1 804-306-00 Analog Test Head J4A J19 804-256-00 800-321-00 TH I/F 879-726 Slot 3 SCS Testhead Analog BP ACISB-B 949-886 J11 TBA 949-824 J4 804-305-00 J4B J20 Terminator Plug 807-358-00 TERMINATOR 879-701 J3 DIGITAL I/F 879-802 Slot 1 UB UB Card Cage J3 5V Paths used to interrogate the Tiger System Configuration 12/02/02

  9. TCIO and STATE BUS to DIGITAL SUBSYSTEM TESTHEAD TCIO State (A/B)(TCIO) PE32s/AUX Slots 44-48 Slots 50-53 804-257-00 Cable 807-425-00 Cable (x4) QSB #1 Slot 49 CSB BACKPLANE J1 Digital Backplane A TC0S TC0D TC1S TC1D TC2S TC2D TC0R TCIR0 TCIR1 TC2R0 TC2R1 DK DK* RCLK RCLK* State_A (0..14) State_B (0..14) TCIO (0..2) TCIO_R (0..2) TSET_A/B SDAT (A/B) STB (A/B) QUAL (A/B) GMASK (A/B) CLK_100MHZ (A/B) RCLK_100MHZ (A/B) FAIL (A/B) CLRFL (A/B) COND (A/B) ADSS (0..5) (A/B) PWRCL BKPLN Rows 67-72 1 PE32s Slots 54-57 Slots 59-62 Test Computer BIF PCI Slot 3 J6 Digital Backplane A QSB #4 Slot 58 CSB Splitter 26 J4 J1 J2 1 J8 Slot 1 Slot 2 26 PE32s/AUX Slots 25-29 Slots 31-34 Digital Backplane B QSB #3 Slot 30 J2 PE32s Slots 35-38 Slots 40-43 Digital Backplane B QSB #2 Slot 39 J3 12/02/02

  10. 807-437-00 Cable PE32s/AUX Slots 44-48 Slots 50-53 100 MHz Rows 33-34 Digital BP A QSB #1 Slot 49 J49 J5 QSB #1 Slot 49 CLK_800MHZ (1..4) PE32s Slots 35-38 Slots 40-43 Digital BP B QSB #2 Slot 39 J6 PE32s/AUX Slots 25-29 Slots 31-34 Digital BP B QSB #3 Slot 30 J7 PE32s Slots 54-57 Slots 59-62 Digital BP A QSB #4 Slot 58 J8 CLOCKS 100 MHz 800 MHz QSB #1 Digital BP A PE32s/AUX Slots 44-48 Slots 50-53 J49 807-426-00 Cables C_CLK_100MHZ C_CLK_100MHZ* 804-336-00 Cable QSB #2 Digital BP B PE32s Slots 35-38 Slots 40-43 10/100 MHZ Reference Module 15 J39 J14 CLK CLK* 14 CSB Slot 1 16 J2 17 18 QSB #3 Digital BP B PE32s/AUX Slots 25-29 Slots 31-34 J30 QSB #4 Digital BP A PE32s Slots 54-57 Slots 59-62 J58 12/02/02

  11. Matrix Paths 12/02/02

  12. 16 16 16 15 15 15 18 18 18 17 17 17 20 20 20 19 19 19 22 22 22 21 21 21 24 24 24 23 23 23 26 26 26 25 25 25 Matrix Pins 2, 46, 47 & 48 to Digital Subsystem Support Cabinet Test Head Analog BP Test Head Digital BP A Test Head Digital BP A Test Head Digital BP B P/O 807-441-00 Cable P/O 807-431-00 Cable Backplane Connections P/O 807-432-00 Cable Xpt 2 S 16 16 Xpt 2 S 16 16 Xpt 2 S 16 16 Xpt 2 S 16 11B P 6 P 1 P 1 P 2 P 1 P 2 UB BP Slot 2 J3 517-301-xx Xpt 2 F 4 15 Xpt 2 F 15 15 Xpt 2 F 15 15 Xpt 2 F 15 11A J13 Xpt 2 G 5, 17 18 Xpt 2 G 18 18 Xpt 2 G 18 18 Xpt 2 G 18 11C J13 J11 J12 TO QSBs PE32s AUX P/O 807-442-00 Cable Xpt 46 S 16 22B 17 Xpt 46 S 17 17 Xpt 46 S 17 17 Xpt 46 S 17 P 1 3 P 2 J23 Xpt 46 F 4 22A 20 Xpt 46 F 20 20 Xpt 46 F 20 20 Xpt 46 F 20 Xpt 46 G 5, 17 22C 19 Xpt 46 G 19 19 Xpt 46 G 19 19 Xpt 46 G 19 Xpt 47 S 19 24B 22 Xpt 47 S 22 22 Xpt 47 S 22 22 Xpt 47 S 22 UB BP Slot 13 J3 517-301-xx Xpt 47 F 7 24A J17 21 Xpt 47 F 21 21 Xpt 47 F 21 21 Xpt 47 F 21 Xpt 47 G 8, 20 24C 24 Xpt 47 G 24 24 Xpt 47 G 24 24 Xpt 47 G 24 Xpt 48 S 22 26B 23 Xpt 48 S 23 23 Xpt 48 S 23 23 Xpt 48 S 23 Xpt 48 F 10 26A 26 Xpt 48 F 26 26 Xpt 48 F 26 26 Xpt 48 F 26 Xpt 48 G 11, 23 26C 25 Xpt 48 G 25 25 Xpt 48 G 25 25 Xpt 48 G 25 PE 32 (Jxx_P6) * AUX (Jxx_P6) * QSB (Jxx_P6) * Xpt 2 S Xpt 2 S A13 A15 Xpt 47 S A9 N/U on TIGER Xpt 2 F Xpt 2 F B-F 13 B-F 15 Xpt 47 F B-H 9 Xpt 2 G Xpt 2 G AA-EE 13 AA-EE 14 AA-EE 15 AA-EE 16 Xpt 47 G AA-GG 9; AA-GG 10 xx = Slot Number Xpt 46 S Xpt 46 S A11 A17 Xpt 48 S A7 Xpt 46 F Xpt 46 F B-F 11 B-F 17 Xpt 48 F B-H 7 Xpt 46 G Xpt 46 G AA-EE 11 AA-EE 12 AA-EE 17 AA-EE 18 Xpt 48 G AA-GG 7 AA-GG 8 12/02/02

  13. MATRIX/CALBUS CONNECTIONS BETWEEN TEST HEAD ANALOG BACKPANE AND DIGITAL BACKPLANES ANALOG BP DIGITAL BP A DIGITAL BP A DIGITAL BP B J23 J13 J11 J12 807-431-00 Cable Backplane 807-432-0 0 Cable Pin Signal ------------------- Pin Signal Connections Pin Signal ------- Pin Signal 1 Alarm ------------------- 1 Alarm ----------------- 1 ALARM* ------- 1 ALARM* 2 Alarm Enable ------------------- 2 Alarm Enable ----------------- 2 ALARM_ENABLE* ------- 2 ALARM_ENABLE* 3 Bsafety ------------------- 3 Bsafety ----------------- 3 BSAFETY* ------- 3 BSAFETY* 4 Shutdown ------------------- 4 Shutdown ----------------- 4 SHUTDOWN* ------- 4 SHUTDOWN* 5 ------------------- 5 ----------------- 5 BRD_INSTALLED ------- 5 BRD_INSTALLED 6 ------------------- 6 ----------------- 6 ------- 6 7 System DGS ------------------- 7 System DGS ----------------- 7 DGS ------- 7 DGS 8 DGS Shield ------------------- 8 DGS Shield ----------------- 8 AGND ------- 8 AGND 9 ------------------- 9 ----------------- 9 DC_CALBUS_HI_F ------- 9 DC_CALBUS_HI_F 10 ------------------- 10 ----------------- 10 DC_CALBUS_HI_S ------- 10 DC_CALBUS_HI_S 11 Dig. Cal HS ------------------- 11 Dig. Cal HS ----------------- 11 DC_CALBUS_LO_S ------- 11 DC_CALBUS_LO_S 12 Dig. Cal HG ------------------- 12 Dig. Cal HG ----------------- 12 DC_CALBUS_HI_G ------- 12 DC_CALBUS_HI_G 13 Dig. Cal HF ------------------- 13 Dig. Cal HF ----------------- 13 DC_CALBUS_LO_G ------- 13 DC_CALBUS_LO_G 14 ------------------- 14 ----------------- 14 DC_CALBUS_LO_F ------- 14 DC_CALBUS_LO_F 15 Dig. Xpt 2 F ------------------- 15 Dig. Xpt 2 F ----------------- 15 DC_MATRIX_2_F ------- 15 DC_MATRIX_2_F 16 Dig. Xpt 2 S ------------------- 16 Dig. Xpt 2 S ----------------- 16 DC_MATRIX_2_S ------- 16 DC_MATRIX_2_S 17 Dig. Xpt 46 S ------------------- 17 Dig. Xpt 46 S ----------------- 17 DC_MATRIX_46_S ------- 17 DC_MATRIX_46_S 18 Xpt 2 G ------------------- 18 Xpt 2 G ----------------- 18 DC_MATRIX_2_G ------- 18 DC_MATRIX_2_G 19 Xpt 46 G ------------------- 19 Xpt 46 G ----------------- 19 DC_MATRIX_46_G ------- 19 DC_MATRIX_46_G 20 Dig. Xpt 46 F ------------------- 20 Dig. Xpt 46 F ----------------- 20 DC_MATRIX_46_F ------- 20 DC_MATRIX_46_F 21 Dig. Xpt 47 F ------------------- 21 Dig. Xpt 47 F ----------------- 21 DC_MATRIX_47_F ------- 21 DC_MATRIX_47_F 22 Dig. Xpt 47 S ------------------- 22 Dig. Xpt 47 S ----------------- 22 DC_MATRIX_47_S ------- 22 DC_MATRIX_47_S 23 Dig. Xpt 48 S ------------------- 23 Dig. Xpt 48 S ----------------- 23 DC_MATRIX_48_S ------- 23 DC_MATRIX_48_S 24 Xpt 47 G ------------------- 24 Xpt 47 G ----------------- 24 DC_MATRIX_47_G ------- 24 DC_MATRIX_47_G 25 Xpt 48 G ------------------- 25 Xpt 48 G ----------------- 25 DC_MATRIX_48_G ------- 25 DC_MATRIX_48_G 26 Dig. Xpt 48 F ------------------- 26 Dig. Xpt 48 F ----------------- 26 DC_MATRIX_48_F ------- 26 DC_MATRIX_48_F 12/02/02

  14. Matrix Crosspoints Mapping and Pin Block/Channel Correlation 12/02/02

  15. 12/02/02

  16. 12/02/02

  17. 12/02/02

  18. 38 35 25 23 13 11 1 A B C D J11 J12 J13 CABLE PE32 Card 48 (Channels 225-256) PE32 Card 50 (Channels 1-32) PE32 Card 51 (Channels 33-64) PE32 Card 52 (Channels 65-96) PE32 Card 53 (Channels 97-128, up to 112 shown) Arrangement of digital channels, by DIB Header (DIB left, view from DUT side) 12/02/02

  19. 38 35 25 23 13 11 1 12/02/02

  20. 12/02/02

  21. 12/02/02

  22. Calibration Paths 12/02/02

  23. CALIBRATION SIGNALS Mainframe UB Backplane 807-441-00 Cable 807-431-00 Cable CAL LGCAL LSCAL LFCAL HGCAL HSCAL HF Dig. Cal. HSense Dig. Cal. HGuard Dig. Cal. HForce UB ASY Slot 21 Testhead Analog Backplane J3 J13 J23 807-432-00 Cable DC_CALBUS_HI_F DC_CALBUS_HI_S DC_CALBUS_LO_S DC_CALBUS_HI_G DC_CALBUS_LO_G DC_CALBUS_LO_F J12 J13 J11 Testhead Digital Backplane B Testhead Digital Backplane A QSB #2 Slot 39 QSB #1 Slot 49 QSB #3 Slot 30 QSB #4 Slot 58 J30 J39 J58 J49 Row 26 Row 26 Row 26 Row 26 Rows 38-40 Rows 38-40 Q_CALTREE_IN(2) Q_CALTREE_IN(4) Q_CALTREE_IN(1) Q_CALRTN_IN(4) Q_CALRTN_IN(1) Q_CALRTN_IN(3) Q_CALRTN_IN(2) Rows 38-40 Rows 38-40 Rows 41-45 Rows 41-45 Rows 41-45 Rows 41-45 Q_CALTREE_IN(3) 807-429-00 Cable 807-436-00 Cable 807-430-00 Cables Signals: P_CAL_TREE(1…9) PE32 Slot 29 1 1 PE32 Slot 34 PE32 Slot 40 1 1 PE32 Slot 35 PE32 Slot 59 1 1 PE32 Slot 54 PE32 Slot 48 1 1 PE32 Slot 53 PE32 Slot 28 PE32 Slot 33 PE32 Slot 41 PE32 Slot 36 PE32 Slot 60 PE32 Slot 55 PE32 Slot 47 PE32 Slot 52 1 1 1 1 1 1 1 1 PE32 Slot 27 PE32 Slot 32 PE32 Slot 42 PE32 Slot 37 PE32 Slot 61 PE32 Slot 56 PE32 Slot 46 PE32 Slot 51 1 1 1 1 1 1 1 1 PE32 Slot 26 1 1 PE32 Slot 31 PE32 Slot 43 1 1 PE32 Slot 38 PE32 Slot 62 1 1 PE32 Slot 57 PE32 Slot 45 1 1 PE32 Slot 50 AUX Slot 25 1 AUX Slot 44 1 12/02/02

  24. Tiger HSD Calibration 12/02/02

  25. REF_CMP_IN (DRIVER/COMPARATOR INTERFACE) REF_CMP_IN REF_DRV_OUT REFERENCE DRIVER AND COMPARATOR REF_DRV_OUT* REF_CMP_OUT REF_DRV_EDGE Q_CALTREE_IN<4..1> QSB TG GENERATOR REF_CMP_OUT* REF_DRV_EDGE* ACISB1_CALTREE_IN (QSB 1 SECTION) Levels for Reference Comparator ACISB2_CALTREE_IN TDR_VMEAS QSB CALTREE ICAL_IN_OUT CALTREE_DUT Q_CALTREE_OUT P_CALTREE<9..1> (QSB SECTION) (CONTROL SECTION) REF_CMP_OUT REF_CMP_OUT* QSB - REFERENCE DRIVER/COMPARATOR & CALTREE P_PPMU_OUT<8..1> (PE32 Input) P_PPMU_REF<8..1> (PE32 Input) DC_MATRIX_46_F QSB THI DC_MATRIX_46_S QSB PPMU SUPPORT REF_CMP_IN DC_MATRIX_46_G V_ICAL_OUT THALOG ACISB_CALBUS_HI_F VBIAS (PPMU SUPPORT) REF_DRV_OUT CALTREE_DUT_OUT CALTREE_DUT ACISB_CALBUS_HI_S REF_DRV_OUT* ACISB_CALBUS_HI_G DRV_CMP_CALTREE DRV_CMP_ICAL_CALTREE (BOARD CONTROLAND CONNECTIONS) TDR_VMEAS ICAL_IN_OUT ICAL_IN_OUT QSB - THI & PPMU SUPPORT 12/02/02

  26. Q_CALTREE_IN<1> Q_CALTREE_1_2 Q_CALTREE_IN<2> Q_CALTREE_IN<3> Q_CALTREE_3_4 Q_CALTREE_IN<4> Q_CALTREE_1_4 ACISB1_CALTREE_IN DRV_CMP_ICAL_CALTREE CALTREE_ACISB_1_2 ACISB2_CALTREE_IN Q_CALTREE_MISC CALTREE_TDRVMEAS TDR_VMEAS P_CALTREE<1> P_CALTREE<2> P_CALTREE_1_2 P_CALTREE<3> P_CALTREE_1_4 P_CALTREE_3_4 P_CALTREE<4> P_CALTREE_5_8 P_CALTREE_LOW P_CALTREE_5_6 P_CALTREE<5> CALTREE_OUT P_CALTREE_9_12 P_CALTREE_7_8 P_CALTREE<6> P_CALTREE_HIGH P_CALTREE<7> P_CALTREE<8> P_CALTREE_9_OPEN P_CALTREE<9> TP101 P_CALTREE_50_GND CALTREE - PE RELAYS (QSB) R 49.9 CALTREE - QUADRANT RELAYS (QSB) 12/02/02

  27. CAL_1_0 CAL<0> CAL_3_0 CAL<1> CAL_3_2 CAL<2> CAL_7_0 CAL<3> CAL_5_4 CAL<4> CAL_7_4 CAL<5> CAL_15_0 CAL_7_6 CAL<6> CAL<7> CAL_9_8 CAL<8> CAL_11_8 CAL<9> CAL_11_10 CAL<10> CAL_15_8 CAL<11> CAL_13_12 CAL<12> CAL_15_12 CAL<13> QSB_CALTREE_COAX (from QSB) CALTREE_OUT CAL_15_14 CAL<14> CAL<15> CAL_17_16 CAL<16> CAL_19_16 CAL<17> CAL_19_18 CAL<18> CAL_23_16 CAL<19> CAL_21_20 CAL<20> CAL_23_20 CAL<21> CAL_31_16 CAL_23_22 CAL<22> CAL<23> CAL_25_24 CAL<24> CAL_27_24 CAL<25> CAL_27_26 CAL<26> CAL_31_24 CAL<27> CAL_29_28 CAL<28> CAL_31_28 CAL<29> CAL_31_30 CAL<30> CAL<31> CALTREE RELAYS (PE32) 12/02/02

  28. V_ICAL_OUT S8 THALOG S7 VBIAS S6 - SYSTEM_DGS S5 ADC_SIG1 + P_PPMU_OUT<4> S4 P_PPMU_OUT<3> S3 THI1_ADC_BUSY P_PPMU_OUT<2> S2 A0 A1 A2 P_PPMU_OUT<1> THI1_ADC_IN THI1 ADC SDATA S1 + To THI1 A/D - Q_DGS THI1_ADC_SCLK S8 Q_DGS S7 Q_DGS S6 - S5 ADC_REF1 P_PPMU_REF<4> + S4 P_PPMU_REF<3> S3 10V A/D REFERENCE P_PPMU_REF<2> S2 P10VREF A0 A1 A2 P_PPMU_REF<1> S1 10V REG THI1_ADC_MUX_SEL<0> P15VA THI1_ADC_MUX_SEL<1> P10VREF THI1_ADC_MUX_SEL<2> 10V REG S8 S7 S6 - QSB_DUT_DGS ADC_SIG2 S5 + P_PPMU_OUT<8> S4 P_PPMU_OUT<7> THI2_ADC_BUSY S3 P_PPMU_OUT<6> S2 P_PPMU_OUT<5> A0 A1 A2 THI2_ADC_IN THI2 ADC SDATA S1 + To THI2 A/D - THI2_ADC_SCLK Q_DGS S8 Q_DGS S7 Q_DGS S6 - S5 ADC_REF2 + P_PPMU_REF<8> S4 P_PPMU_REF<7> S3 P_PPMU_REF<6> S2 P_PPMU_REF<5> A0 A1 A2 S1 THI2_ADC_MUX_SEL<0> THI2_ADC_MUX_SEL<1> QSB THI CONNECTIONS - ANALOG MUXES - ADC THI2_ADC_MUX_SEL<2> 12/02/02

  29. KF Vih Vil Voh Comp Out FAIL LOGIC Comp Out Vol CHOUT DCL_OUT < > DOUT < > Vclh KDUT Iol Vcll VCP LOAD CTRL R 301K Ioh CAL_IND < > CHAN_TEE < > CAL < > DOUT_ALARM < > KP DC_MTX_F <3..0> KA KMF ALARM < > Vppmu PPMU_CH < > KPPMU FALCON DCL AND CHANNEL RELAYS (PE32) PPMU Meas Out 12/02/02

  30. KDUT Vih CH. DATA INPUT KF Vil Voh Comp Out (closed) Comp Out Vol 301K Iol VCP LOAD CTRL Ioh CAL PPMU KPPMU DC MTX FORCE KMF ALARM KA PPMU Calibration Path (PE32) 12/02/02

  31. 100K 100K 40 40 10K 10K 1K 1K -15VA +15VA ICAL_IN_OUT TDR_VMEAS V_ICAL_OUT ACISB_CALBUS_HI_F DC_MATRIX_46_F ACISB_CALBUS_HI_S VBIAS DC_MATRIX_46_S THALOG LJC MATRIX -15VA +15VA PPMU - CURENT CALIBRATION CIRCUIT (QSB) 12/02/02

  32. DUT_ALARM ALARM R Vih Vclh FUNCTIONAL DUT Driver Vcll Vil PARAMETRIC PPMU Voh PPMU DC_FORCE Vol DC SUBSYSTEM MUX MATRIX DCMS Ioh DYNAMIC LOAD Iol DC_SENSE Vcp CAL PE Board QSB Vih, Vil, Voh, Vol Calibration, PPMU Calibration 12/02/02

  33. Kms Kmf DRV V/I Source S1 (UBVI) XPT depends upon Digital Channel (2,46,47 or 48) CMP Test Head Digital BP B Test Head Digital BP A Test Head Digital BP A Test Head Analog BP CMP Kmd F 807-441-00 J 1 2 J 1 1 J 1 3 J 2 3 J 1 3 UB BP Slot 2 517-301 807-432-00 807-431-00 System Voltmeter Xpt 2 S Kdut Kf A/D 807-442-00 J 1 7 UB BP Slot 13 517-301 Vppmu Kp Xpt 46 - 48 PPMU 1 DGS TATS Card Cage PPMU MEAS OUT 1 Kppmu1 32 PPMU 2 Kppmu2 CALTREE MUX SEL 949-873 QSB DGS PPMU 32 PE32 Kppmu32 DGS Oct 1 DGS Oct 2 DATA OUT Gain and Level Shift A/D MUX PPMU Meas 1 PPMU Meas 2 949-873 QSB Oct & Bd SELECT QSB A/D Calibration - Voltmeter 12/02/02

  34. Vih DRV Vil Test Head Digital BP B Test Head Digital BP A Test Head Digital BP A Test Head Analog BP 807-441-00 J 1 2 J 1 1 J 1 3 J 2 3 J 1 3 UB BP Slot 2 517-301 Matrix Sense 807-432-00 807-431-00 System Voltmeter Xpt 2 Kdut Kf A/D 807-442-00 J 1 7 UB BP Slot 13 517-301 Vppmu Kp Xpt 46 - 48 Matrix Sense PPMU 1 DGS TATS Card Cage Kms Kmf Kppmu1 PPMU MEAS OUT 1 32 PPMU 2 Kppmu2 CALTREE MUX SEL 949-873 QSB DGS PPMU 32 PE32 Kppmu32 DGS Oct 1 DGS Oct 2 DATA OUT Gain and Level Shift A/D MUX PPMU Meas 1 PPMU Meas 2 949-873 QSB Oct & Bd SELECT Vih/Vil Calibration CMP CMP 12/02/02

  35. Vih DRV Vil Voh CMP Test Head Digital BP B Test Head Digital BP A Test Head Digital BP A Test Head Analog BP CMP Vol 807-441-00 J 1 2 J 1 1 J 1 3 J 2 3 J 1 3 UB BP Slot 2 517-301 Matrix Sense 807-432-00 807-431-00 System Voltmeter Xpt 2 Kdut Kf A/D 807-442-00 J 1 7 UB BP Slot 13 517-301 Vppmu Kp Xpt 46 - 48 Matrix Sense PPMU 1 DGS TATS Card Cage Kms Kmf Kppmu1 PPMU MEAS OUT 1 32 PPMU 2 Kppmu2 CALTREE MUX SEL 949-873 QSB DGS PPMU 32 PE32 Kppmu32 DGS Oct 1 DGS Oct 2 DATA OUT Gain and Level Shift A/D MUX PPMU Meas 1 PPMU Meas 2 949-873 QSB Oct & Bd SELECT Voh/Vol Calibration 12/02/02

  36. DRV Test Head Digital BP B Test Head Digital BP A Test Head Digital BP A Test Head Analog BP Vclh Vcll 807-441-00 J 1 2 J 1 1 J 1 3 J 2 3 J 1 3 UB BP Slot 2 517-301 Matrix Sense 807-432-00 807-431-00 System Voltmeter Xpt 2 Kdut Kf A/D 807-442-00 J 1 7 UB BP Slot 13 517-301 Vppmu Kp Xpt 46 - 48 Matrix Sense PPMU 1 DGS TATS Card Cage Kms Kmf I=+/- Kppmu1 PPMU MEAS OUT 1 32 PPMU 2 Kppmu2 CALTREE MUX SEL 949-873 QSB DGS PPMU 32 PE32 Kppmu32 DGS Oct 1 DGS Oct 2 DATA OUT Gain and Level Shift A/D MUX PPMU Meas 1 PPMU Meas 2 949-873 QSB Oct & Bd SELECT Vclh/Vcll Calibration CMP CMP 12/02/02

  37. DRV Test Head Digital BP B Test Head Digital BP A Test Head Digital BP A Test Head Analog BP Iol=xmA 807-441-00 J 1 2 J 1 1 J 1 3 J 2 3 J 1 3 UB BP Slot 2 517-301 Matrix Sense 807-432-00 807-431-00 Vcp System Voltmeter Xpt 2 Kdut Ioh=xmA Kf A/D 807-442-00 J 1 7 UB BP Slot 13 517-301 Vppmu Kp Xpt 46 - 48 Matrix Sense PPMU 1 DGS TATS Card Cage Kms Kmf I=0mA Kppmu1 PPMU MEAS OUT 1 32 PPMU 2 Kppmu2 CALTREE MUX SEL 949-873 QSB DGS PPMU 32 PE32 Kppmu32 DGS Oct 1 DGS Oct 2 DATA OUT Gain and Level Shift A/D MUX PPMU Meas 1 PPMU Meas 2 949-873 QSB Oct & Bd SELECT Vcp Calibration CMP CMP 12/02/02

  38. DRV CMP CMP PE CALTREE Iol Vcp Ioh Kp Kf Other Channels PE32 100K 10K 100K 1K 10K 40 PE RELAYS QSB RELAYS 1K Other PE32s - 40 MUX A/D + DGS DGS+2.5V Other QSBs QSB #1 Ioh/Iol Calibration 12/02/02

  39. DH Edge being compared by the GVOH comparator and the compare signal measured by the TCMU (Timing Calibration Measurement Unit). The path starts at the Per Pin Deskew adjustment, running thru the Event Logic, Precondition, and Linearization RAM. Then it goes into the EG4, thru the DH verniers, Drive Polarity, and out the Data Formatter as DP. Next is the FALCON, where DP goes into the Driver, swinging back thru the comparator in to the Mux Logic on the EG4. Then the Pulse Width Adjustment is applied and the Compare Data path is taken onto the Cal Return, which brings us to QSB1, into the ARK and many muxes. The path proceeds thru Measure ME to the Front End and finally into the TCMU. TMS QSB1 DRV_TG Reference Driver Edge ACISB TRIG Reference Driver TRIG Measure Me MPC SDAT DIB TCMU Enable Griffin and R R Front PPMU Vector ADC ARK STB and Missing Control Data End Logic Edge TREF Latch Cal Return Data TCMU and Cntrl TREF ADC Other Cal Reference ACISB1 Returns Comp Latch Comparator EXT_DRV_TG ACISB2 HSD_SYNC_OUT Misc. PPMU (Cal Resistors) QSB Select (x2) PE9 User Scope Sync PE Open Select (x4) 50 Ohm Load R Short Edge Type Event Cells Per Pin Deskew PE Edge Timing Caltree DIB External Instruments Event Cell Data IOL Relays VT I/O Format Event Steering Logic DH a/b PPMU IOH DH/DL Precondition Linearization RAM Relay MCon DE Relay DP Trim From QSB through DACs DH/DL Driver FunCon DUT Con Drive Polarity Logic VIH DH/DL a/b Relay Relay Data Formatter DH/DL Verniers VIL PE32 VOH Compare Data GVOH Cal Return Format MUX Logic GVOH/LVOL Pulse Width Adjust CH GVOH LVOL QSB CL LVOL VOL Fixed Neg Prot Clamp VCL Z Clamps VCH EDGE PLACEMENT CALIBRATION Fixed Pos Prot Clamp 12/02/02

  40. TMS QSB 1 DRV_TG Reference Driver Edge Reference ACISB Driver TRIG TRIG DIB SDAT MPC Measure ME PPMU R R Griffin Vector Data ADC TCMU Enable and CTRL ARK Front Missing ACISB1 and End Edge Logic STB Latch CAL RETURN Misc. ACISB2 TREF Data TCMU Other Cal Returns QSB & TREF CNTRL Select ADC Reference (x2) Comparator Comp Latch PE9 EXT_DRV_TG Open HSD_SYNC_OUT PE Select 50 Ohm (x4) Load R User Scope Sync Short DIB External Instruments Edge Event PE Caltree DH a/b IOL Timing Data Relays Event Per Pin DH/DL Linearization From Vcp Logic Adj . Precondition RAM QSB thru PPMU DACs Relay IOH MCon Relay DE DH/DL DH/DL Drive DH/DL DP DP a/b Data Polarity Trim Verniers Formatter Logic VIH FunCon DUT Con From Relay Relay VIL QSB thru VOH DACs GVOH GVOH/LVOL CAL Return DH EDGE MUX Pulse Width Format Logic Adjust Calibration LVOL EG4 (QSB) QSB VOL PE32 12/02/02

  41. A/D A/D REF_CMP_IN P_CALTREE<1> REF_DRV_OUT P_CALTREE_1_2 CALTREE_DUT Q_CALTREE_IN<1> P_CALTREE<2> REF_DRV_OUT* P_CALTREE_1_4 P_CALTREE_3_4 P_CALTREE<3> Q_CALTREE_1_2 ICAL_IN_OUT Q_CALTREE_IN<2> To Other QSBs via 807-429-00 QSB to QSB, Cal. Cable P_CALTREE_LOW P_CALTREE_5_8 Q_CALTREE_IN<3> Q_CALTREE_1_4 P_CALTREE_5_6 P_CALTREE<4> Q_CALTREE_3_4 P_CALTREE_9_12 To PE32s via 807-430-00 QSB to PE32 CALTREECable DRV_CMP_ICAL_CALTREE Q_CALTREE_IN<4> CALTREE_OUT P_CALTREE<5> P_CALTREE_7_8 Q_CLATREE_MISC ACISB1_CALTREE_IN P_CALTREE_HIGH P_CALTREE<6> CALTREE_ACISB_1_2 ACISB2_CALTREE_IN P_CALTREE_9_OPEN P_CALTREE<7> P_CALTREE_50_GND CALTREE_TDRMEAS P_CALTREE<8> TDR_VMEAS P_CALTREE<9> TP101 49.9 Ohms QSB CAL<0> CAL_1_0 CAL<1> CAL_3_0 CAL<2> CAL_3_2 CAL<3> Test Head Digital BP B Test Head Digital BP A Test Head Digital BP A Test Head Analog BP CAL_7_0 CAL<4> CAL_5_4 CAL<5> J 1 2 J 1 1 J 1 3 J 2 3 J 1 3 UB BP Slot 2 517-301 807-432-00 807-441-00 807-431-00 CAL<6> CAL_7_4 CAL_7_6 CAL_15_0 CAL<7> KDUT KF Vppmu CAL<8> J 1 7 807-442-00 UB BP Slot 13 517-301 CAL_9_8 CAL<9> KP CAL_11_8 CAL<10> Matrix Sense PPMU 1 DGS CAL_11_10 CAL<11> TATS Card Cage KMF CAL<12> CAL_15_8 CAL_13_12 CAL<13> KPPMU1 CAL<14> CAL CALTREE_OUT CAL_15_12 CAL_15_14 CAL<15> QSB_CALTREE_COAX PPMU MEAS OUT 1 CAL<16> CAL_17_16 CAL<17> CAL_19_16 PPMU Meas 1 CAL<18> PPMU 2 CAL_19_18 PPMU Meas 2 32 KPPMU2 CAL<19> CAL_23_16 CAL<20> MUX SEL CAL_21_20 Gain and Level Shifter CAL<21> MUX CAL<22> DGS CAL_23_20 CAL_23_22 DGS Oct 1 PPMU 32 CAL<23> KPPMU32 DGS Oct 2 CAL<24> CAL_25_24 CAL_31_16 CAL<25> CAL_27_24 Oct & Bd Select 949-873 QSB CAL<26> CAL_27_26 PE32 CAL<27> CAL<28> CAL_31_24 CAL_29_28 CAL<29> CAL<30> CAL_31_28 CAL_31_30 12/02/02 CAL<31>

  42. Digital Power 12/02/02

  43. System Node Front Panel P/O 807-476-00 Cable 866-156-00 Cable QSBs (SMC Node) MAP-110 Power Supply 405-376-00 SYS NODE P2 P3 P1 P2 J10 + 5V J-PWR +5V SYS NODE P5 Testhead Digital Backplane A J19 (Located in top BAY 1) P/O 807-440-01 Cable PE32s (SMC Node) 807-477-00 Cable P1 P2 Support Cabinet Node J24 SMC PWR SUPPLY (On top of PDU) 405-223-00 +24V J20 +/- 5V & +/- 5V RTN +24V QSBs (SMC Node) Testhead Digital Backplane B P4 J10 804-182-00 Cable J20 48VDC Busbar P1 P2 JC- LON CDU NODE PE32s (SMC Node) 24V / LON Testhead Digital Backplane A & B Busbar Digital Power Supplies -2.5V* +0.8V* -5.2V -2.0V +5.0V -3.6V 3.3V* Analog Power Supplies +15V -15V -10V +15V CDU CABINET 48VDC 807-423-00 PDU Side Panel DC1-DC4 QSB 807-423-00 Digital Power Supplies -2.0V +0.8V** -2.5V** -3.6V -5.2V 3.3V** Analog Power Supplies +5.0V +10V -5.0V +15V FRM QSB 807-423-00 807-423-00 -10V Digital Power Supplies -2.0V +0.8V* -2.5V* -3.6V -5.2V 3.3V* Analog Power Supplies +5.0V +10V -5.0V +15V -10V DPE32 ** The 3.3V is developed as -2.5V + 0.8V PE32 DC VOLTAGES TO THE TESTHEAD DIGITAL BACKPLANE AND DIGITAL BOARDS 12/02/02 * The 0.8v is developed as 3.3 - 2.5V

  44. Board Installed Signal Flow 12/02/02

  45. P6 J10 J12 P2 3 3 BD_INST_I 5 5 Test Head Digital Backplane B 949-882-00 P/O 807-440-01 Cable J25 J26…J27...J28 J29 J30 J31...J32...J33 J34 J35 J36..J37..J38 J39 J40..J41..J42 807-432-00 J43 P3 Cable J C - T H BDS_IN_C AUX PE32 QSB #3 PE32 PE32 QSB #2 PE32 4 1 5 1 5 1 5 1 5 1 5 1 5 1 5 BDS_IN_M 5 J44 J45 J46...J47...J48 J49 J50...J51...J52 J53 J54 J55...J56...J57 J58 J59...J60...J61 J62 2 6 2 6 2 6 2 6 2 6 2 6 2 6 3 7 3 7 3 7 3 7 3 7 3 7 3 7 AUX PE32 QSB #1 PE32 PE32 QSB #4 PE32 4 8 4 8 4 8 4 8 4 8 4 8 4 8 1 5 1 5 1 5 1 5 1 5 1 5 1 5 2 6 2 6 2 6 2 6 2 6 2 6 2 6 J25_PFILL J29_PFILL J30_PFILL J34_PFILL J35_PFILL J39_PFILL J43_PFILL P7 J9 3 7 3 7 3 7 3 7 3 7 3 7 3 7 J11 P1 4 8 4 8 4 8 4 8 4 8 4 8 4 8 3 3 BD_INST_I 5 5 J44_PFILL J45_PFILL J49_PFILL J53_PFILL J54_PFILL J58_PFILL J62_PFILL Test Head Digital Backplane A 949-881-00 Notes: 1. When board is installed in slot, a 0 ohm resistor is connected between the input and output. 2. The total resistance measured between J9-3 and J10-3 isxxxx ohms when all boards are installed. 1 4 Jxx_PFILL Connector 2 1 10 9 34 37 P6, P7 P3 807-440-01 Cable “P” connector layouts Board_Installed Signal Flow ON CDU 12/02/02

  46. TJA Inputs from HSD 12/02/02

  47. PE32 QSB #1 TMS A TMS BTMS E P1 Slot 45 PE #5 807-433-00 Cable P2 TMS A Row 45 Slot 46 PE #6 TMS B Slot 47 PE #7 Slot 48 PE #8 TMS E Slot 50 PE #1 Rows 28-30 (J49-P10) Slot 51 PE #2 TMS ATMS BTMS E Slot 52 PE #3 Slot 53 PE #4 Slot 49 QSB #2 PE32 TMS A TMS BTMS E TMS A Slot 35 PE #9 P1 807-433-00 Cable P2 Slot 36 PE #10 TMS B Row 48 Slot 37 PE #11 Slot 38 PE #12 TMS E 866-107-00 Cable P1 Slot 40 PE #13 P2 Rows 28-30 (J39-P10) A TJA PACS CAGE 949-861-00 Slot 41 PE #14 TMS ATMS BTMS E J 2 B Slot 42 PE #15 Slot 43 PE #16 Slot 39 E TMB 1 SCS CAGE Slot 22 Rows 62-64 QSB #3 PE32 TMS A TMS BTMS E Slot 26 TMS A P1 P2 PE #17 807-433-00 Cable Row 51 949-782-00 Slot 27 PE #18 TMS B PE #19 Slot 28 TMS E Slot 29 PE #20 Slot 31 PE #21 Rows 28-30 (J30-P10) Slot 32 PE #22 TMS ATMS BTMS E Slot 33 PE #23 Slot 34 PE #24 Slot 30 QSB #4 PE32 TMS A TMS BTMS E Slot 54 PE #29 P2 807-433-00 Cable TMS A P1 Row 59 Slot 55 PE #30 TMS B Slot 56 PE #31 TMS E Slot 57 PE #32 Slot 59 PE #25 Rows 28-30 (J58-P10) Slot 60 PE #26 TMS ATMS BTMS E Slot 61 PE #27 Slot 62 PE #28 Slot 58 Row 38 40 43 P2 P3 P4 807-320-01 Cable P1 Rows 75-79 TMB #2 SCS CAGE Slot 20 949-782-00 TJA Inputs from High Speed Digital 12/02/02

  48. Digital Cable Diagram 12/02/02

  49. 807-430-00 (x4) TH DIG BP A or B J53 J54 (A) J35 J34 (B) Row 1 804-257-00 TH DIG BP A J49 (QSB 1) J58 (QSB 4) Rows 41-45 TH DIG BP B J39 (QSB 2) J30 (QSB 3) Rows 41-45 Test Computer BIF PCI Slot 3 J2 CSB BP Slot 1 Row 67-72 CAL TREE TCIO TH DIG BP A or B J52 J55 (A) J36 J33 (B) Row 1 804-336-00 CSB Slot 1 Row 14 10/100 MHz Ref J14 TH DIG BP A or B J51 J56 (A) J37 J32 (B) Row 1 PPCLK100 TH DIG BP A or B J50 J57 (A) J38 J31 (B) Row 1 804-337-00 CSB BP Slot 1 Row 23 PACS II CLK100 TH DIG BP A or B J48 J59 (A) J40 J29 (B) Row 1 Linear BB +15V CSB BP Slot 1 Row 145 807-202-00 TH DIG BP A or B J47 J60 (A) J41 J28 (B) Row 1 Linear BB -15V TH DIG BP A or B J46 J61 (A) J42 J27 (B) Row 1 807-425-00 CSB BP Slot 2 J6 Row 1 TH DIG BP A J1 TH DIG BP A or B J45 J62 (A) J43 J26 (B) Row 1 807-425-00 CSB BP Slot 2 J6 Row 26 TH DIG BP B J2 TH DIG BP A/B J44(A) J43 J25(B) Row 1 807-425-00 CSB BP Slot 2 J8 Row1 TH DIG BP B J3 807-425-00 807-431-00 TH ANA BP J23 TH DIG BP A J13 CSB BP Slot 2 J8 Row26 TH DIG BP A J4 Matrix (xpt 2,46,47,48) CAL; DGS; Safety;Shutdown STATE A/B TCIO CLK 807-432-00 TH DIG BP A J11 TH DIG BP B J12 807-426-00 CSB BP Slot 1 J2 Row 15 DC_CALBUS; DGS; Matrix (xpt 2,46,47,48) Safety; Shutdown TH DIG BP A J49 807-426-00 CSB BP Slot 1 J2 Row 16 TH DIG BP A J58 807-433-00 (x4) 807-426-00 TH DIG BP A/B J30,J39,J49,J58 Rows 28-30 SCS BP Slot 22 Row 45,48,51,59 CSB BP Slot 1 J2 Row 17 TH DIG BP B J30 TMS A, B, E 807-426-00 CSB BP Slot 1 J2 Row 18 TH DIG BP B J39 807-434-00 CLK100 TH DIG BP A J49 Row 35 CTRL PNL HSD SYNC TH DIG BP A J49 Row 31 HSD SYNC 807-435-00 TH ANA BP J11 Row 10 CSB BP Slot 1 J2 Row 6 807-427-00 TH DIG BP A J49 Row 37 Cal Tree; THADS SCS BP Slot 20 TMB 2 or Slot 22 TMB 1 Row 40 TMS Start TH ANA BP J12 Row 10 RCLK/FFAIL CSB BP Slot 2 J7 Row 1 or Row 4 TH DIG BP A J58 Row 26 CSB BP Slot 1 J2 Row 52 or Row 163 807-428-00 807-436-00 TH DIG BP A J49 Row 26 TH DIG BP B J39 Row 26 PACS BP #1 Slot 8 row 40 or row 98 STATEA/B CALRTN TH DIG BP B J30 Row 26 TH DIG BP A J58 Rows 38-40 TH DIG BP A J5 807-429-00 807-437-00 TH DIG BP A J49 Rows 38-40 TH DIG BP B J39 Rows 38-40 TH DIG BP B J6 TH DIG BP A J49 Rows 33-34 TH DIG BP B J7 CALTREE TH DIG BP B J30 Rows 38-40 CLK_800 MHz TH DIG BP A J8 12/02/02

  50. Digital and AC signal card pin outs 12/02/02

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