Programmable Logic

Programmable Logic

Inputs Dense array of Dense array of AND gates Product OR gates terms Outputs Prgrammable Logic Organization • Pre-fabricated building block of many AND/OR gates (or NOR, NAND) • "Personalized" by making or breaking connections among the gates Programmable Array Block Diagram for Sum of Products Form

ORGANIZATION PAL PROM PLA AND ARRAY PROG. FIXED PROG. OR ARRAY FIXED PROG. PROG. Basic Programmable Logic Organizations • Depending on which of the AND/OR logic arrays is programmable, we have three basic organizations

F0 = A + B C F1 = A C + A B F2 = B C + A B F3 = B C + A Inputs Outputs Product t erm F F F F A B C 0 1 2 3 0 1 1 0 A B 1 1 - Reuse 0 0 0 1 B C - 0 1 of 0 1 0 0 A C 1 - 0 t erms 1 0 1 0 B C - 0 0 1 0 0 1 A 1 - - PLA Logic Implementation Key to Success: Shared Product Terms Equations Example: Personality Matrix Input Side: 1 = asserted in term 0 = negated in term - = does not participate Output Side: 1 = term connected to output 0 = no connection to output

B C A F3 F0 F2 F1 PLA Logic Implementation Example Continued – Un-programmed device All possible connections are available before programming

B C A AB BC AC BC A F3 F0 F2 F1 PLA Logic Implementation Unwanted connections are "blown" Note: some array structures work by making connections rather than breaking them

AB Notation for implementing F0 = A B + A B F1 = C D + C D CD CD CD+CD AB+AB PLA Logic Implementation Unprogrammed device • Alternative representation for • high fan-in structures • Short-hand notationso we don't • havetodraw all the wires! • X at junction indicatesa connection A B C D Programmed device AB

A C B ABC A B C A B C ABC ABC ABC ABC ABC ABC ABC F1 F2 F3 F4 F5 F6 PLA Logic Implementation Multiple functions of A, B, C F1 = A B C F2 = A + B + C F3 = A B C F4 = A + B + C F5 = A  B  C F6 = A  B  C

PALs and PLAs • What is difference between Programmable Array Logic (PAL) and • Programmable Logic Array (PLA)? • PAL concept — implemented by Monolithic Memories • - AND array is programmable, OR array is fixed at fabrication A given column of the OR array has access to only a subset of the possible product terms PLA concept — Both AND and OR arrays are programmable

PALs and PLAs • Of the two organizations the PLA is the most flexible • One PLA can implement a huge range of logic functions • BUT many pins; large package, higher cost • PALs are more restricted / you trade number of OR terms vs number of outputs • Many device variations needed • Each device is cheaper than a PLA

A B C D W X Y Z A A AB AB 0 0 0 0 0 0 0 0 00 01 11 10 00 01 11 10 0 0 0 1 0 0 0 1 CD CD 0 0 1 0 0 0 1 1 00 0 0 X 1 00 0 1 X 0 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 01 0 1 X 1 01 0 1 X 0 0 1 0 1 1 1 1 0 D D 0 1 1 0 1 0 1 0 0 1 X X 0 0 X X 11 11 0 1 1 1 1 0 1 1 C C 1 0 0 0 1 0 0 1 10 10 1 0 0 1 1 0 0 0 0 1 X X 0 0 X X 1 0 1 0 X X X X 1 0 1 1 X X X X B B 1 1 0 0 X X X X K-map for W K-map for X 1 1 0 1 X X X X 1 1 1 0 X X X X A A 1 1 1 1 X X X X AB AB 00 01 11 10 00 01 11 10 CD CD 00 0 1 X 0 00 0 0 X 1 X 01 01 0 1 0 0 X 0 1 D D 1 1 X X 0 1 X X 11 11 C C W = A + B D + B C X = B C Y = B + C Z = A B C D + B C D + A D + B C D 10 10 1 1 X X 1 0 X X B B K-map for Y K-map for Z PAL Logic Implementation K-maps Design Example: BCD to Gray Code Converter Truth Table Minimized Functions:

A B C D A BD BC 0 BC W = A + B D + B C X = B C Y = B + C Z = A B C D + B C D + A D + B C D 0 0 0 B C 0 0 A B C D BCD AD BCD W X Y Z PAL Logic Implementation Minimized Functions:

A A A 1 B 4 C B D 2 3 W D B 3 C B 2 D C 4 Z D 1 D 5 A B 2 X 1 B 1 C 3 C D C 1: 7404 hex inverters 2 Y B 1 B 2,5: 7400 quad 2-input NAND 3: 7410 t ri 3-input NAND 4: 7420 dual 4-input NAND PAL Logic Implementation Code Converter Discrete Gate Implementation 4 SSI Packages vs. 1 PLA/PAL Package!

A B C D A A AB AB ABCD 00 01 11 10 00 01 11 10 CD CD 00 00 1 0 0 0 0 1 1 1 ABCD 01 01 0 1 0 0 1 0 1 1 ABCD D D ABCD 11 11 0 0 1 0 1 1 0 1 C C 10 10 0 0 0 1 1 1 1 0 AC AC B B K-map for EQ K-map for NE BD A A BD AB AB 00 01 11 10 00 01 11 10 CD CD ABD 00 00 0 0 0 0 0 1 1 1 BCD 1 0 0 0 0 0 1 1 01 01 ABC D D 11 1 1 0 1 11 0 0 0 0 BCD C C 10 1 1 0 0 10 0 0 1 0 B B K-map for L T K-map for GT EQ NE LT GT PLA Logic Implementation Another Example: Magnitude Comparator

Complex Programmable Logic Devices • Complex PLDs typically combine PAL combinational logic with FFs • Organized into logic blocks • Fixed OR array size • Combinational or registered output • Some pins are inputs only • Usually enough logic for simple counters, state machines, decoders, etc. • e.g. 22G10, 20V8, etc.

Field Programmalble Gate Arrays (FPGAs) • FPGAs have much more logic than CPLDs • 2K to >10M equivalent gates • Requires different architecture • FPGAs can be RAM-based or Flash-based • RAM FPGAs must be programmed at power-on • External memory needed for programming data • May be dynamically reconfigured • Flash FPGAs store program data in non-volitile memory • Reprogramming is more difficult • Holds configuration when power is off

FPGA Structure • Typical organization in 2-D array • Configurable logic blocks (CLBs) contain functional logic • Combinational functions plus FFs • Complexity varies by device • CLB interconnect is either local or long line • CLBs have connections to local neighbors • Horizontal and vertical channels use for long distance • Channel intersections have switch matrix • IOBs (I/O logic Blocks) connect to pins • Usually have some additional C.L./FF in block

IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB IOB FPGA Structure Input/Output Block IOB IOB IOB IOB CLB CLB CLB CLB Switch Matrix SM SM SM CLB CLB CLB CLB SM SM SM CLB CLB CLB CLB Configurable Logic Block SM SM SM CLB CLB CLB CLB

Programmable Logic