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The FC16 Forth Core

The FC16 Forth Core. Lab 7 Module F4.1. Lab 7. Data Stack Instructions. Hex Opcode. Name. Function. 0000. NOP. No operation. 0001. DUP. Duplicate T and push data stack. N <= T; N2 <= N;. 0002. SWAP. Exchange T and N. T <= N; N <= T;. 0003. DROP. Drop T and pop data stack.

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The FC16 Forth Core

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  1. The FC16 Forth Core Lab 7 Module F4.1

  2. Lab 7

  3. Data Stack Instructions Hex Opcode Name Function 0000 NOP No operation 0001 DUP Duplicate T and push data stack. N <= T; N2 <= N; 0002 SWAP Exchange T and N. T <= N; N <= T; 0003 DROP Drop T and pop data stack. T <= N; N <= N2; 0004 OVER Duplicate N into T and push data stack. T <= N; N <= T; N2 <= N; 0005 ROT Rotate top 3 elements on stack clockwise. T <= N2; N <= T; N2 <= N; 0006 -ROT Rotate top 3 elements on stack counter-clockwise. T <= N; N <= N2; N2 <= T; 0007 NIP Drop N and pop rest of data stack. T is unchanged. N <= N2; 0008 TUCK Duplicate T into N and push rest of data stack. N2 <= T; 0009 ROT_DROP Drop N2 and pop rest of data stack. T and N are unchanged. Equivalent to ROT DROP 000A ROT_DROP_SWAP Drop N2 and pop rest of data stack. T and N are exchanged. Equivalent to ROT DROP SWAP

  4. Hex Opcode Name Function Funit16 Instructions (fcode = lower 6 bits of opcode) 0010 + Pop N and add it to T. 0011 - Pop T and subtract it from N. 0012 1+ Add 1 to T 0013 1- Subtract 1 from T 0014 INVERT Complement all bits of T. 0015 AND Pop N1 and AND it to T. 0016 OR Pop N1 and AND it to T. 0017 XOR Pop N1 and AND it to T. 0018 2* Logic shift left T. 0019 U2/ Logic shift right T. 001A 2/ Arithmetic shift right T. 001B RSHIFT Pop T and shift N1 T bits to the right. 001C LSHIFT Pop T and shift N1 T bits to the left. 001D mpp multiply partial product (used for multiplication) 001E shldc shift left and decrement conditionally (used for division)

  5. Code Name Function 0020 TRUE Set all bits in T to ‘1’. 0021 FALSE Clear all bits in T to ‘0’. 0022 NOT 0= TRUE if all bits in T are ‘0’. 0023 0< TRUE if sign bit of T is ‘1’. 0024 U> T <= TRUE if N > T (unsigned), else T <= FALSE 0025 U< T <= TRUE if N < T (unsigned), else T <= FALSE 0026 = T <= TRUE if N = T, else T <= FALSE 0027 U>= T <= TRUE if N >= T (unsigned), else T <= FALSE 0028 U<= T <= TRUE if N1 <= T (unsigned), else T <= FALSE 0029 <> T <= TRUE if N /= T, else T <= FALSE 002A > T <= TRUE if N1 > T (signed), else T <= FALSE 002B < T <= TRUE if N1 < T (signed), else T <= FALSE 002C >= T <= TRUE if N1 >= T (signed), else T <= FALSE 002D <= T <= TRUE if N1 <= T (signed), else T <= FALSE Funit16 Instructions (cont.) (fcode = lower 6-bits of opcode)

  6. Code Name Function 0030 >R “To-R” Pop T and push it on return stack. 0031 R> “R-from” Pop return stack R and push it into T. 0032 R@ “R-fetch” Copy R to T and push register stack 0033 R>DROP “R-from-drop” Pop return stack R and throw it away 0034 @ Fetch the byte at address T in RAM and load it into T 0035 ! Store the byte in N at the address T. Pop both T and N. 0036 ROM@ Fetch the byte at address T in ROM and load it into T. 0037 S@ Fetch the 8-bit byte from Port S and load it into T. 0038 DIG! Write the 4 hex digits in T to the digit register DigReg 0039 LD! Store T to the LED register LDreg. Return Stack, Memory Access, and I/O Instructions

  7. Code Name Function 0040 LIT Load inline literal to T and push data stack. 0041 JMP Jump to inline address 0042 JZ Jump if all bits in T are ‘0’ 0043 DRJNE Decrement R and jump if R is not zero 0044 CALL Call subroutine 0045 RET Subroutine return 0046 JB1LO Jump if input pin B1 is LO 0047 JB2LO Jump if input pin B2 is LO 0048 JB3LO Jump if input pin B3 is LO 0049 JB4LO Jump if input pin B4 is LO 004A JB1HI Jump if input pin B1 is HI 004B JB2HI Jump if input pin B1 is HI 004C JB3HI Jump if input pin B1 is HI 004D JB4HI Jump if input pin B1 is HI Literal and Transfer Instructions

  8. Multiplication and Division Instructions

  9. Multiplication 1101 x1011 1101 1101 100111 0000 100111 1101 10001111 13 x11 13 13 143 = 8Fh

  10. Multiplication 1101 x1011 1101 1101 100111 0000 100111 1101 10001111 1101 00001011 01101101 adsh 1101 10011110 adsh 1001111 sh 1101 10001111 adsh

  11. Multiplication UM* ( u1 u2 -- upL upH ) T N N2 mpp (multiply partial product) if N(0) = 1 then adsh else sh end if; : UM* ( u1 u2 - upL upH ) 0 4 FOR mpp NEXT ROT_DROP ; All other signed and unsigned multiplication can be derived from UM*

  12. 16 x 16 = 32 Multiply Instruction : UM* ( u1 u2 - upL upH ) 0 16 FOR mpp NEXT ROT_DROP ;

  13. Testing Multiply Instruction : MAIN ( -- ) BEGIN waitB4 S@ \ get u1LO waitB4 S@ \ get u1HI waitB4 S@ \ get u2LO waitB4 S@ \ get u2HI waitB4 UM* \ multiply DIG! \ display upH waitB4 DIG! \ display upL AGAIN ;

  14. variable AVector: STD_LOGIC_VECTOR (width downto 0); variable BVector: STD_LOGIC_VECTOR (width downto 0); variable CVector: STD_LOGIC_VECTOR (width downto 0); variable yVector: STD_LOGIC_VECTOR (width downto 0); variable y_tmp: STD_LOGIC_VECTOR (width-1 downto 0); variable y2_tmp: STD_LOGIC_VECTOR (width-1 downto 0); variable yvec0: STD_LOGIC; begin AVector := '0' & a; BVector := '0' & b; CVector := '0' & c; y_tmp := false; y2_tmp := false; yVector := '0' & false;

  15. mpp (multiply partial product) if N(0) = 1 then adsh else sh end if; when "11110" => -- mpp if b(0) = '1' then yVector := AVector + CVector; else yVector := AVector; end if; y <= yVector(width downto 1); y2 <= yVector(0) & b(width-1 downto 1); T N N2

  16. Division 10 1010 13 135 13 05 1101 10000111 1101 00111 0000 01111 1101 00101 0000 0101

  17. Division 8-bit/4-bit = 4:4 1010 numer[8:0] denom[3:0] _10000111 1101 1101 10000111 1101 00111 0000 01111 1101 00101 0000 0101 If denom < numer[7:4] then overflow (quotient won’t fit in 4 bits) Let T = numer[8:4] N = numer[3:0] N2 = denom[3:0]

  18. Division 8-bit/4-bit = 4:4 T N 1010 sll 100001110 1101 1101 10000111 1101 00111 0000 01111 1101 00101 0000 0101 N2 for I in 0 to 3 loop sll T & N; if T[8:4] > N2 then T := T - (0 & N2); N(0) := ‘1’; end if; end loop;

  19. sub1sll 001111110 1101 sll 011111100 1101 001011010 sub1sll rem quot Division 8-bit/4-bit = 4:4 T N 1010 sll 100001110 1101 1101 10000111 N2 1101 00111 0000 01111 1101 00101 0000 0101

  20. Division N2 N T : UM/MOD ( unumL unumH udenom -- urem uquot ) N2 N T -ROT 4 FOR SHLDC NEXT denom quot rem ROT_DROP_SWAP ; All other signed and unsigned division operations can be derived as WHYP words from UM/MOD

  21. when "11111" => -- shldc yVector := a & b(width-1); y2_tmp := b(width-2 downto 0) & '0'; if yVector > CVector then yVector := yVector - CVector; y2_tmp(0) := '1'; end if; y <= yVector(width-1 downto 0); y2 <= y2_tmp; for I in 0 to 3 loop sll T & N; if T[8:4] > N2 then T := T - (0 & N2); N(0) := ‘1’; end if; end loop; T N sll 100001110 1101 N2

  22. 32 / 16 = 16:16 Division : UM/MOD ( unL unH ud -- ur uq ) -ROT 16 FOR shldc NEXT ROT_DROP_SWAP ;

  23. Testing Divide Instruction : MAIN ( -- ) BEGIN waitB4 S@ \ get unLLO waitB4 S@ \ get unLHI waitB4 S@ \ get unHLO waitB4 S@ \ get unHHI waitB4 S@ \ get udLO waitB4 S@ \ get udHI waitB4 UM/MOD \ divide Dig! \ display uq waitB4 Dig! \ display ur AGAIN ;

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