Chapter 9: Serial Communication Interface – SCI

1. Chapter 9: Serial Communication Interface – SCI The HCS12 Microcontroller Han-Way Huang Minnesota State University, Mankato September 2009

2. Why Serial Communication? • Parallel data transfer requires many I/O pins. This requirement prevents the microcontroller from interfacing with as many devices as desired in the application. • Many I/O devices do not have high data rate to justify the use of parallel data transfer. • Data synchronization for parallel transfer is difficult to achieve over a long distance. This requirement is one of the reasons that data communications are always using serial transfer. • Cost consideration • What is SCI? • An interface designed to transfer data only in asynchronous mode that utilizes the EIA- 232 standard.

3. Asynchronous Serial Data Communication • Often used in data communication between a DTE and a DCE with or without a modem. • DTE stands for data terminal equipment and can be either a computer or a terminal. • DCE stands for data communication equipment. A modem is a DCE. • A basic data communication link is shown in Figure 9.0. • There are three kinds of data communication links: • 1. Simplex link • 2. Half-duplex link • 3. Full-duplex link

4. Types of communication link configuration • The RS232 Standard • Was the most widely used physical level interface for data communication • Specifies 25 interchange circuits for DTE/DCE use • Established in 1960 by Electronics Industry Association (EIA) • Revised to RS232C in 1969 • Revised to RS232D in 1987 • Revised to RS232E in 1992 and renamed as EIA-232-E • Revised and renamed to TIA-232F in 1997 • there are four aspects: electrical, functional, procedural, and mechanical.

5. The EIA-232E Electrical Specifications • The interface is rated at a signal rate of < 20 kbps • The signal can transfer correctly within 15 meters • The maximum driver output voltage (with circuit open) is -25 V to +25 V • The minimum driver output voltage (loaded output) is -25 V to -5 V and +5 V to +25 V • The minimum driver output resistance when power is off is 300 W • The receiver input voltage range is -25 V to +25 V • The receiver output is high when input is open circuit • A voltage more negative than -3 V at the receiver input is interpreted as a logic 1 • A voltage more positive than +3 V at the receiver input is interpreted as a logic 0

7. Mechanical Specification

8. Data format for asynchronous data communication • Data is transmitted character by character bit-serially • A character consists of • 1. one start bit (0), • 2. 7 to 8 data bits, • 3. an optional parity bit, • 4. one, or one and a half, or two stop bits (1) • 5. least significant bit is transmitted first • 6. most significant bit is transmitted last

9. How to Detect the Arrival of Start Bit? • Use a clock signal with frequency at least 16 times that of the data rate to sample the RxD signal. • When the RxD pin is idle (high) for at least three sampling times and a falling edge follows, the SCI circuit checks the third, fifth, and seventh samples after the first sample. If the majority of them are low, then the start bit is considered detected. • How to Determine the Logic Value of a Data Bit? • Use a clock signal with frequency at least 16 times that of the data rate to sample the • incoming data. • Take the majority function of the eighth, ninth, and tenth samples. If the majority of them are 1s, then the logic value is determined to be 1.

10. Example 9.1Sketch the output of the letter g when it is transmitted using the format of one start bit, 8 data bit, and 1 stop bit. Solution: The ASCII code of letter g is $67 or %01100111. This code will be followed by a stop bit. The output from the DTE should be:

11. The HCS12 SCI Subsystem • A HCS12 device may have one or two serial communication interface. These two SCI • interfaces are referred to as SCI0 and SCI1. • The block diagram is shown in Figure 9.7. • The SCI uses the data format of one start, eight or nine data bits, and one stop bit. The • collection of the start bit, eight or nine data bits, and the stop bit is called a frame. • The SCI function supports parity checking. This option requires the use of 9-bit data • format. • One SCI channel uses two signal pins from Port S. The SCI0 shares the use of • PS0 (RxD0) and PS1 (TxD0), whereas SCI1 shares the use of PS2 (RxD1) and PS3 (TxD1). • The SCI has the capability to send break to attract the attention of the other party of communications. • A break is defined as the transmission or reception of logic 0 for a frame or longer time. • The SCI supports hardware parity for transmission and reception. • The SCI supports idling line and address mark wakeup, which is useful in multi-drop • environment to reduce the software overhead.

13. Baud Rate Generation • The HCS12 SCI module uses a 13-bit counter to generate this clock signal. This circuit is called baud rate generator. • The baud rate generator divides down the E clock to derive the clock signal for reception and transmission. • The user writes an appropriate value into the SCIxBDH and SCIxBDL (x = 0 or 1) register pair to set the baud rate.

14. The value to be written into the baud rate generator register is the rounding of the • following expression: • SBR = fE 16  baud rate

15. The SCI Control Registers

17. SCI Status Registers

19. Character Transmission • The block diagram of the SCI transmitter is shown in Figure 9.11. • To transmit a character from the SCI module, the user writes the data bits into the • SCIxDRH and SCIxDRL registers. • The data bits in SCIxDRH and SCIxDRL registers will be transferred to the transmit shift • register and shifted out serially from the TxD pin. • Each time the SCI transfers data from the buffer SCIxDRH/L to the transmit shift register, • it also sets the TDRE flag in the SCIxSR1 register. • The setting of the TDRE flag indicates that the MCU can write new data into the SCI data • register. • When the transmit shift register is not transmitting data, the TxD signal goes to idle state. • When both the transmit data registers and shift register are empty, the TC flag in • the SCIxSR1 register is set to 1. • An interrupt may be requested to the MCU if the TDRE or TC flag is set to 1.

21. Character Reception • The block diagram of the SCI receiver is shown in Figure 9.14. • The SCI receiver can handle either 8- or 9-bit characters. • When receiving 9-bit data, the R8 bit of the SCIxDRH register holds the ninth bit. • During an SCI reception, the receive shift register shifts in a frame from the RxD pin. • After a complete frame is shifted into the receive shift register, the data portion of the • frame is transferred to the SCI data register. The receive data register full flag in the • SCIxSR1 register is set to 1. • An interrupt may be requested to the MCU if it is enabled.

23. Single-Wire Operation • In this operation, the RxD pin is disconnected from the SCI module. • The SCI module uses the TxD pin for both receiving and transmitting as illustrated in • Figure 9.15. • Single-wire operation is enabled by setting the LOOPS and the RSRC bits in the • SCIxCR1 register. • Setting the LOOPS bit disables the path from the RxD pin to the receiver. Setting the • RSRC bit connects the receiver input to the output of the TxD pin driver. • Both transmitter and receiver must be enabled. • The TXDIR bit determines whether the TxD pin is going to be used as an input (TXDIR • = 0) or output (TXDIR = 1) in this mode of operation.

24. Flow Control of UART in Asynchronous Mode • The SCI module will transmit data as fast as the baud rate allows. • In some circumstances, the software may not be able to read data as fast as the data is • received. • There is a need for the MCU to tell the transmitting device to suspend transmission of • data temporarily. • Similarly, the HCS12 may need to be told to suspend transmission temporarily. This is • done by flow control. • There are two common methods of flow control: XON/XOFF and hardware. • XON/XOFF is implemented completely in software but requires a full-duplex • communication. • When incoming data needs to be suspended, am XOFF byte is transmitted back to the • other device that is transmitting. • To start the other device transmitting again, an XON character is transmitted. • The XON and XOFF characters have the ASCII code of 0x11 and 0x13, respectively. • Hardware flow control requires the use of extra signals. Generally, an input pin of the • transmitter is controlled by the receiver. • Before transmitting any character, the transmitter needs to test the flow control input pin.

25. Example 9.2Write an instruction sequence to configure the SCI0 to • operate with the following parameters: • 9600 baud (E clock is 24 MHz) • one start bit, 8 data bits, one stop bit • no interrupt • address mark wakeup • disable wakeup initially • long idle line mode • enable transmit and receive • no loop back • disable parity checking • Solution: The following instruction sequence will configure the SCI0 properly: • movb #$00,SC0BDH ; set up baud rate • movb #156,SC0BDL ; “ • movb #$4C,SC0CR1 ; select 8 data bits, address mark wakeup • movb #$0C,SC0CR2 ; enable transmitter and receiver

26. Example 9.4Write a subroutine to output the character in accumulator A to the SCI0 channel using the polling method. Solution: - The subroutine will wait until the bit 7 of SCI0SR1 register is set before sending out the character in accumulator A. #include "c:\miniide\hcs12.inc" putcSCI0 brclr SCI0SR1,TDRE,* ; wait for TDRE to be set staa SCI0DRL ; output the character rts void putcSCI0 (char cx) { while (!(SCI0SR1 & TDRE)); SCI0DRL = cx; }

27. Example 9.5Write a subroutine to read a character from SCI0 using the polling method. Return the character in accumulator A. Solution: #include "c:\miniide\hcs12.inc" getcSCI0 brclr SCI0SR1,RDRF,* ; wait until RDRF bit is set ldaa SCI0DRL ; read the character rts char getcSCI0 (void) { while(!(SCI0SR1 & RDRF)); return (SCI0DRL); }

28. Example 9.6 Write a subroutine to output a string pointed to by index register X to the SCI0using the polling method. • Solution: • This subroutine will call putcSCI0( ) repeatedly until all characters have been sent. putsSCI0 ldaa 1,x+ ; get a character and move the pointer beq donep ; is this the end of the string jsr putcSCI0 bra putsSCI0 donep rts void putsSCI0 (char *cx) { while (!(*cx)) { putcSCI0(*cx); cx++; } }

29. Example 9.7 Write a subroutine to input a string from SCI0. The string is terminated by the carriage return character and must be stored in a buffer pointed to by index register X. • Solution: • This subroutine will call getcSCI0( ) repeatedly until the carriage return character is getsSCI0 jsrgetch cmpa #CR ; is it a carriage return beqqi staa 0,x ; save the character and increment the pointer jsrputch ; echo it back to SCI0 cmpa #BS ; is it a backspace character? (ASCII code is 0x08) bnenc ; no, continue dex ; decrement the input buffer pointer ldaa #WS ; wipe out the previous character (ASCII code of WS is 0x20) jsrputch ldaa #BS jsrputch bra gets ncinx bra gets qiclr 0,x ; terminate the string by a NULL character rts

30. int gets(char *ptr){ char cx; while ((cx = getch()) != 0x0D) { *ptr = cx; putch(cx); if (cx == 0x08) { // is it a backspace character? ptr--; // move back the string pointer putch(0x20);// output a space putch(0x08);// output another backspace character } ptr++; // move buffer pointer } *ptr = 0; // terminate the string with a NULL character return 0;}