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ModelSim Seminar

ModelSim Seminar . Jonathan Distler CPU Architecture - VHDL 20/08/07. Objectives. Presentation: Course website – Forum Introduction to VHDL Entities – Architectures – Configurations Generic variables – Generate loops Wave generation and analysis ModelSim Simulation

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ModelSim Seminar

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  1. ModelSim Seminar Jonathan Distler CPU Architecture - VHDL 20/08/07

  2. Objectives • Presentation: Course website – Forum • Introduction to VHDL • Entities – Architectures – Configurations • Generic variables – Generate loops • Wave generation and analysis • ModelSim Simulation • Practice with VHDL and ModelSim • First Assignment Definitions

  3. Presentation ברוכים הבאים לקורס ארכיטקטורת CPU מרצה: פרופ' הוגו גוטרמן עוזר הוראה: יונתן דיסטלר שעות קבלה: כל 24 היממה באתר http://hl2.bgu.ac.il ניתן למצוא אותי כפי שפורסם בסילבוס.

  4. Introduction to VHDL • You’ve already been induced and introduced • Nevertheless… lets practice: • What’s an entity? • What kind of architectures do you know? • What is hierarchy? • What’s a configuration good for? • What’s a generic variable? • What’s a generation loop? • Let us analyze some wave transportations… Don’t forget the difference between a signal and a variable

  5. How to use ModelSim? • Change “current directory” (“File->Change directory”) • Add a new “work” library (“File->New->Library”) • Open new .vhd files and edit them • Compile all the .vhd files according to their dependence!!!(“Compile”) • Load the“test bench” configuration file. (double-click on the configuration link of the complied test bench) • Add a new wave window (“File->New->Window->Wave”)

  6. How to use ModelSim? (cont’) • Copy the relevant signals to the wave window • Work the right way… so u won’t loose grade: • Change their names to “Display Names” • Use “Dividers” • Mark time periods • Zoom into the right signals • Use Hexa notations when necessary • Run the wave every “x” period of time • Save the wave format to use it later (or if the computer crashes) !!! (“File->Save”: waveExample.do)

  7. Practice Practice Practice • Download the seminar files, compile them and run the test bench • Are there any propagation delays? • Download the advanced files and ask yourselves the same question…

  8. First Assignment • Look for it at http://hl2.bgu.ac.il • Be serious and do what you are asked to • Use the VHDL book • else, use the forum and ask yourselves • else, use the forum and ask me • else, come to see me, and I’ll tell you to use the VHDL book • Use only the given files, DO NOT create logic gates by your own. All the modules must be structural, based on the files we gave you, assuming a 1ns delay every time it is asked for.

  9. Good luck! Any questions?

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