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Decisions Behind the Design: LabVIEW for CompactRIO Sample Projects

Decisions Behind the Design: LabVIEW for CompactRIO Sample Projects. Meghan Kerry Embedded Software Product Manager Certified LabVIEW Developer (CLD). Agenda. Keys to quality in a software architecture Software architecture overview I/O safe states Watchdog timers Message communication

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Decisions Behind the Design: LabVIEW for CompactRIO Sample Projects

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  1. Decisions Behind the Design: LabVIEW for CompactRIO Sample Projects Meghan Kerry Embedded Software Product Manager Certified LabVIEW Developer (CLD)

  2. Agenda • Keys to quality in a software architecture • Software architecture overview • I/O safe states • Watchdog timers • Message communication • Error handling • System monitoring

  3. Keys to Quality in a Software Architecture • Define software architecture and identify architecture components • Create an architectural diagram • Consider key components such as data communication, error handling, etc. • Learn the foundational design patterns • Create new design patterns as required by your application (requires experience)

  4. Data Communication Diagram • Documents foundational components: • Processes (loops) • Data communication paths • Type of data transfer

  5. Data Communication Types

  6. Typical CompactRIO System Diagram

  7. LabVIEW for CompactRIO Sample Projects • Pre-built architectures for embedded control and monitoring applications • Designed to ensure quality and scalability of a system

  8. Basic FPGA Diagram Performs deterministic and/or high speed control

  9. State Machine for Hardware I/O and Control

  10. Failure Conditions that Initiate Safe States • Examples (from Fail Safe Reference Design): • RT Safe – indicates the RT system is ready • Emergency Safe – tied to an emergency shut-off switch • Watchdog Safe – monitors the Real-Time system • Control Inputs Valid – monitors the inputs to the control algorithm • Based on system requirements

  11. Basic FPGA Diagram Detects software failures Recovers from software failures

  12. Watchdogs • A watchdog timer is a hardware counter that interfaces with the embedded software application to detect and recover from software failures • A user can then: • Reboot real-time target automatically • Perform user-defined recovery actions • Two types of watchdogs with NI Real-Time hardware: • LabVIEW Real-Time Watchdog • Real-Time <-> FPGA Watchdog (FPGA Fail Safe Design)

  13. LabVIEW Real-Time Only Watchdog • Uses hardware timer built into CompactRIO hardware • “Reset = True” reboots system if the watchdog process is starved

  14. LabVIEW Real-Time Watchdog • Enable occurrence in expiration actions • Configure appropriate watchdog timeout and Watchdog Whack loop period

  15. Real-Time <-> FPGA Watchdog Reset timer Put control loop into a safe state, and reset system

  16. Real-Time <-> FPGA Watchdog • Pet the watchdog at a user-defined watchdog pet rate • This resets the counter implemented in the FPGA VI See Fail-Safe Control Reference Design whitepaper

  17. Basic FPGA Diagram - Summary Detects software failures Recovers from software failures Performs deterministic and/or high speed control

  18. Basic Real-Time Processor Diagram Communicates messages with client Sends messages to other processes or targets Periodically communicates tags

  19. Constructing a Message Examples Data Variant allows data-type to vary. Different messages may require different data Command String constant allows user to specify message

  20. Queued Message Handler API

  21. Queued Message Handler Framework Command Parser Queued Message Handler Setup Message handling loop Watchdog Loop Monitoring Loop

  22. Queued Message Handler Framework One or more messages handled per case Command Parser Communicate messages between processes or targets Watchdog Loop Monitoring Loop

  23. Basic Real-Time Processor Diagram Handles all error messages from FPGA and RT target

  24. Error Messages • Specific Error Handling • Code called in specific locations to respond with an action to specific error codes • Possible actions are retry, ignore, correct • Central Error Handling • High-level code that checks for errors in an entire system • Responds to classes of errors rather than specific codes • Uses the classification to determine which actions to take Queue Central Handler

  25. Central Error Handling Framework Command Receiver Loop Specific Handler UI message handling loop Watchdog Loop Specific Handler Monitoring Loop Specific Handler

  26. Central Error Handling Framework Command Receiver Loop Specific Handler Watchdog Loop Specific Handler Monitoring Loop Specific Handler

  27. Central Error Handling Framework Return classification of error Handle classified errors (update FPGA state and/or reboot system) Get next error based on priority Log and send all errors to UI

  28. Basic Real-Time Processor Diagram Communicates messages with client

  29. Sending Commands Across the Network • Network Streams are great for commands because are they are lossless • Tips: • Use Flush with zero timeout to minimize latency • Add code to handle UI disconnections (see Sample Project)

  30. System Monitoring Embedded processors have limited…. Disk Space RAM CPU Bandwidth LostData Crash Starvation EFFECT

  31. System Monitoring Current value data can be sent to UI with Shared Variables Monitor CPU usage per core Execute loop periodically

  32. Network Published Shared Variables • When to use the Static API: • Small number of variables (less than a dozen) • When to use the Programmatic API: • Iterate through a large number of variables • Dynamically change the IP address of the cRIO from the client (client side only)

  33. Basic Real-Time Processor Diagram Communicates messages with client Sends messages to other processes or targets Periodically communicates tags

  34. Basic HMI Diagram Processes UI Events and communicates messages with real-time system Generates UI Events using the Event Structure Periodically updates UI

  35. Common Variant Architectures • Other LabVIEW for CompactRIO Sample Projects • LabVIEW FPGA Control • LabVIEW FPGA Control with Real-Time Sequencer Engine • LabVIEW Real-Time Control (RIO Scan Interface) • LabVIEW FPGA Waveform Acquisition and Logging • LabVIEW Data Logging and Supervisory Control

  36. FPGA Control with Sequencer Sample Project

  37. Real-Time Control Sample Project

  38. FPGA Waveform Acquisition and Logging

  39. Demo – LabVIEW FPGA Control Sample Project

  40. LabVIEW for CompactRIO Sample Projects • Available in LabVIEW 2012 and later • Find more best practices at ni.com/compactriodevguide

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