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Memory Testing and Pattern Introduction

Memory Testing and Pattern Introduction. TM. Contents. Brief Introduction Memory Classification and Application How to Test Memory IC Pattern Introduction Scramble. Memory IC Testing. For storage media (memory): not magnetic tape, not hard/floppy disk, not brain

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Memory Testing and Pattern Introduction

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  1. Memory Testing and Pattern Introduction TM

  2. Contents • Brief Introduction • Memory Classification and Application • How to Test Memory IC • Pattern Introduction • Scramble

  3. Memory IC Testing • For storage media (memory): • not magnetic tape, not hard/floppy disk, not brain • For silicon process: • not WAT test, not reliability test, • not physical failure analysis • For IC testing: • not logic (ASIC, CPU, FPGA, LCD driver, …) • not mix-signal (ADC, DAC, USB, …) • For test program: • not timing, not pin format, not hardware configuration • not command to generate report, not user interface • We focus on: • electrical failure analysis, (memory IC) function test, test pattern

  4. Memory Classification • Volatile memory: data will lose after power off • SRAM (static random access memory): • Low Power (or Low Voltage) SRAM / High Speed SRAM • DRAM (dynamic RAM, need refresh): • Synchronous DRAM / Double Data Rate (DDR) SDRAM • FCRAM (FJ, Fast Cycle RAM): DRAM cell with SRAM peripheral • Non volatile memory: data still keep after power off • ROM (read only memory) / PROM (programmable ROM) • EPROM (Erasable PROM) / EEPROM (Electrical EPROM) • Flash • Embedded Memory : • some of above memories are merged with some logical purpose circuit on a chip

  5. Memory Application • LP-SRAM: mobile phone • HS-SRAM: cache memory • DRAM: phase out • SDRAM / DDR SDRAM: mother board / graphic card • ROM / PROM / EPROM: game machine / BIOS • EEPROM / Flash: smart card / voice recorder • FCRAM(FJ): mobile phone

  6. Special Testing Feature • SRAM: typical memory function (Write and Read) • DRAM: row and column address are multiplexed, need refresh • SDRAM: need one synchronous clock, pipe-line (burst) concept • DDR SDRAM: one cycle two data, write latency, DLL on/off • FCRAM: need some test mode to access the DRAM cell • ROM: need SOM (source only memory) board of tester, read only • EEPROM / Flash: read / program / erase all / page mode • address and data are multiplexed, BUSY signal • Embedded Memory: in general, several hundreds pins, so we need customer provide more detailed or confidential document about • the memory-related, only around fifty pins information to run a • specified sequence to enter the direct access mode

  7. From the PC BIOS’s View • For the PC with 256M bytes SDRAM (the simplest way, mail box) • write all 0x00, read all 0x00 be visited 2 times • write all 0xFF, read all 0xFF be visited 2 times • write all 0x55, read all 0x55 be visited 2 times • write random, read random be visited 2 times, total 8 times

  8. What We Say the “Testing” • For the 16Mx8 bits SDRAM • 1. In general, when we are debugging or creating a pattern, • we always just consider one DQ only. • 2. In order to get good fault coverage and measure almost all the • device feature listed on data sheet, a test program will access • each bit more than several hundreds times, not only few times DQ1 to DQ8 are accessed in the same time for every address

  9. Elements of Pattern • the most important is address and data:

  10. Pattern Classification • For written data (background data): • solid 0/1, row bar, column bar, checker board, • diagonal, DQ switch, RWI (repeat with invert) • For cell visiting sequence (address changing): • write-verify, scan X/Y, march4n, march6n, • inverse, address complement, RWI • Take too long time and less use • galloping, butter-fly, shift diagonal --- n^2 • For DRAM special: • disturb, Long RAS

  11. Background Data • In testing world: X is ROW is WL (word line), • Y is COLUMN is BL (bit line)

  12. DQ Switch (polarity)

  13. X-Fast vs. Y-Fast

  14. Write Solid1 and RWI

  15. Scan vs. Write Verify

  16. Scan to March-4n

  17. March-6n

  18. Data / Address Scramble • Data scramble: only for DRAM, caused by Bit Line and /BL • Address scramble: in general, DRAM simple, SRAM complex

  19. Display Scramble • Display scramble: whole chip address decoding rule • or chip architecture and DQ sequence • describe the relationship between the electrical address • and topological (physical) address

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