1 / 53

Chapter 05 Tutorial Using HDL Based Design

Chapter 05 Tutorial Using HDL Based Design. Verilog Language. Objective. This tutorial will give you exposure to using HDL based design Using Verilog and Modelsim for simulating the functional design

xiomara-lamorena
Télécharger la présentation

Chapter 05 Tutorial Using HDL Based Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Chapter 05Tutorial Using HDL Based Design Verilog Language

  2. Objective • This tutorial will give you exposure to using HDL based design • Using Verilog and Modelsim for simulating the functional design • This tutorial shows you how to create, using Verilog, a simple combinational logic circuit design

  3. Logic Function F=(x&~y)|(y|z)

  4. Logic Circuit 6

  5. Implementation Methods • Method 1: Using the automatic module generator • Method 2: Using the user free input

  6. Method 1 • Using the automatic module generator

  7. Create a New Project

  8. Enter a Name and Location for the Project

  9. Select the Device and Design Flow for the Project

  10. Create a New Source

  11. Select Verilog Module and Enter File Name

  12. Define Verilog Source

  13. New Source Information

  14. Finish

  15. Next Step

  16. Input Logic Function

  17. Add Test Bench Source

  18. Add Test Bench Waveform

  19. Select Source File

  20. New Source Information

  21. Initialize Timing

  22. Waveform Created by HDL Bencher

  23. Save the Waveform

  24. View Behavioral Text Fixture

  25. Simulate Behavioral Model

  26. ModelSim Windows

  27. Wave Window

  28. Verifying the Logic Function F=(x & ~y)|(y|z)

  29. Question and Answer

  30. Method 2 • Using the user free input

  31. Design a Logic Circuit 6

  32. Create a New Project 2

  33. Enter a Name and Location for the Project 3

  34. Create a New File 4

  35. Free Input Verilog Language in the New File 5

  36. Design Using RTL Level 7

  37. Design Using Gate Level 8

  38. Save the Design 9

  39. File Name: “complogic1.v” • Module nameand File name must the same. 10

  40. Add Source into the Project 11

  41. Select “complogic1.v” 12

  42. Choose Source Type 13

  43. Add New Source for Test Bench Waveform 14

  44. Select Test Bench Waveform 15

  45. Initialize Timing 16

  46. Waveform Created by HDL Bencher 17

  47. Giving Input Values 18

  48. Save the Waveform 19

  49. Select “View Behavioral..” and Run 20

  50. See a HDL Test bench 21

More Related