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Chapter 11

Chapter 11. The SR latch. A timing diagram for the SR latch. A sequence of clock pulses. The clocked SR flip-flop. A timing diagram of the clocked SR flip-flop. The master-slave SR flip-flop. Timing detail of a single clock pulse. Timing detail of a single clock pulse (Cont’d).

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Chapter 11

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  1. Chapter 11

  2. The SR latch

  3. A timing diagram for the SR latch

  4. A sequence of clock pulses

  5. The clocked SR flip-flop

  6. A timing diagram of the clocked SR flip-flop

  7. The master-slave SR flip-flop

  8. Timing detail of a single clock pulse

  9. Timing detail of a single clock pulse (Cont’d) • t1: Isolate slave from master • t2: Connect master to input • t3: Isolate master from input • t4: Connect slave to master

  10. A timing diagram of the master-slave SR flip-flop

  11. The characteristic table for the SR flip-flop

  12. The state transition diagram for an SR flip-flop

  13. The characteristic table for the JK flip-flop

  14. The JK flip-flop

  15. The D flip-flop

  16. The characteristic table for the T flip-flop

  17. The T flip-flop

  18. A general sequential network

  19. Excitation tables for the four basic flip-flops • Please click on the following link Programs\c11t08.GIF to view the excitation tables.

  20. Block diagram of the Pep/7 computer

  21. A 4-bit register

  22. Main memory • Please click on the following link Programs\c11f26.gif to view the main memory diagram.

  23. The data section of the Pep/7 CPU • Please click on the following link Programs\c11f27.gif to view the data section.

  24. The 16 functions of the Pep/7 ALU

  25. The 32 8-bit registers in the data section

  26. Interconnection of the 32 registers

  27. The arithmetic logic unit

  28. The ALU shift and rotate functions at Level LG1

  29. Pseudocode description of the von Neumann execution cycle

  30. The control sequence for the fetch and increment part of the von Neumann cycle for a unary instruction

  31. The control sequence for STBYTA with direct addressing

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