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Progettazione di circuiti e sistemi VLSI

Progettazione di circuiti e sistemi VLSI. Anno Accademico 2010-2011 Lezione 5 15/18.3.2011 L’inverter CMOS. The CMOS Inverter: A First Glance. V. DD. V. V. in. out. C. L. V. DD. CMOS Inverter. N Well. PMOS. 2 l. Contacts. Out. In. Metal 1. Polysilicon. NMOS. GND.

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Progettazione di circuiti e sistemi VLSI

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  1. Progettazione di circuiti e sistemi VLSI Anno Accademico 2010-2011 Lezione 5 15/18.3.2011 L’inverter CMOS L'Inverter CMOS

  2. The CMOS Inverter: A First Glance V DD V V in out C L L'Inverter CMOS

  3. V DD CMOS Inverter N Well PMOS 2l Contacts Out In Metal 1 Polysilicon NMOS GND L'Inverter CMOS

  4. Two Inverters Share power and ground Abut cells Connect in Metal L'Inverter CMOS

  5. V V DD DD R p V out V out R n V V V 0 = = in DD in CMOS InverterFirst-Order DC Analysis VOL = 0 VOH = VDD VM = f(Rn, Rp) L'Inverter CMOS

  6. CMOS Inverter: Transient Response V V DD DD t = f(R .C ) pHL n L R p = 0.69 R C n L V out V out C L C L R n V 0 V V = = in DD in (a) Low-to-high (b) High-to-low L'Inverter CMOS

  7. Voltage TransferCharacteristic L'Inverter CMOS

  8. I Dn V = V +V in DD GSp I = - I Dn Dp V = V +V out DD DSp V out I I I Dp Dn Dn V =0 V =0 in in V =1.5 V =1.5 in in V V V DSp DSp out V =-1 GSp V =-2.5 GSp V = V +V V = V +V in DD GSp out DD DSp I = - I Dn Dp PMOS Load Lines L'Inverter CMOS

  9. CMOS Inverter Load Characteristics L'Inverter CMOS

  10. CMOS Inverter VTC L'Inverter CMOS

  11. Switching Threshold as a function of Transistor Ratio 1.8 1.7 1.6 1.5 1.4 (V) 1.3 M V 1.2 1.1 1 0.9 0.8 0 1 10 10 /W W p n L'Inverter CMOS

  12. Determining VIH and VIL V out V OH V M V in A simplified approach V OL V V IL IH L'Inverter CMOS

  13. Inverter Gain L'Inverter CMOS

  14. Simulated VTC l VIL=1.03 VIH=1.45 NMH=1.05 NML=1.03 L'Inverter CMOS

  15. Gain=-1 Gain as a function of VDD L'Inverter CMOS

  16. 2.5 2 Good PMOS Bad NMOS 1.5 Nominal (V) out Good NMOS Bad PMOS V 1 0.5 0 0 0.5 1 1.5 2 2.5 V (V) in Impact of Process Variations L'Inverter CMOS

  17. Propagation Delay L'Inverter CMOS

  18. CMOS Inverter Propagation DelayApproach 1 L'Inverter CMOS

  19. CMOS Inverter Propagation DelayApproach 2 L'Inverter CMOS

  20. V DD PMOS Metal1 Polysilicon NMOS CMOS Inverters 1.2 m m =2l Out In GND L'Inverter CMOS

  21. Transient Response ? tp = 0.69 CL (Reqn+Reqp)/2 tpHL tpLH L'Inverter CMOS

  22. Design for Performance • Keep capacitances small • Increase transistor sizes • watch out for self-loading! • Increase VDD (????) L'Inverter CMOS

  23. Delay as a function of VDD L'Inverter CMOS

  24. NMOS/PMOS ratio tpHL tpLH tp b = Wp/Wn L'Inverter CMOS

  25. Inverter Sizing Due inverter in cascata  CL=(Cdp1+Cdn1)+ (Cgp2+Cgn2) + CW= (1+β)(Cdn1+Cgn2) +Cw  tp=(tpHL +tpLH)/2=0.69 CL(Reqn+Reqp)/2 = =0.345 ((1+β)(Cdn1+Cgn2) +CW) Reqn(1+r/β) dove r=Reqp/Reqn con stesse dimensioni PMOS e NMOS per δtp/δβ= 0 βopt=sqrt (r (1+ CW/(Cdn1+Cgn2))) L'Inverter CMOS

  26. Inverter Chain In Out CL • If CL is given: • How many stages are needed to minimize the delay? • How to size the inverters? • May need some additional constraints. L'Inverter CMOS

  27. - - 1 1 æ ö æ ö W W N P ç ÷ ç ÷ = = = R R R R R ç ÷ ç ÷ P unit unit N W W W è ø è ø unit unit Inverter Delay • Minimum length devices, L=0.25mm • Assume that for WP = 2WN =2W • same pull-up and pull-down currents • approx. equal resistances RN = RP • approx. equal rise tpLH and fall tpHL delays • Analyze as an RC network 2W W tpHL = (ln 2) RNCL tpLH = (ln 2) RPCL Delay (D): Load for the next stage: L'Inverter CMOS

  28. Inverter with Load Delay RW CL RW Load (CL) tp = kRWCL k is a constant, equal to 0.69 Assumptions: no load -> zero delay Wunit = 1 L'Inverter CMOS

  29. Inverter with Load CP = 2Cunit Delay 2W W Cint CL Load CN = Cunit Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load) L'Inverter CMOS

  30. Delay Formula Cint = gCgin withg 1 f = CL/Cgin- effective fanout R = Runit/W ; Cint =WCunit tp0 = 0.69RunitCunit L'Inverter CMOS

  31. Apply to Inverter Chain In Out CL 1 2 N tp = tp1 + tp2 + …+ tpN L'Inverter CMOS

  32. Optimal Tapering for Given N • Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N • Minimize the delay, find N - 1 partial derivatives • Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 • Size of each stage is the geometric mean of two neighbors • each stage has the same effective fanout (Cout/Cin) • each stage has the same delay L'Inverter CMOS

  33. Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Effective fanout of each stage: Minimum path delay L'Inverter CMOS

  34. Example In Out CL= 8 C1 1 f f2 C1 CL/C1 has to be evenly distributed across N = 3 stages: L'Inverter CMOS

  35. Optimum Number of Stages For a given load, CL and given input capacitance Cin Find optimal sizing f For g = 0, f = e, N = lnF L'Inverter CMOS

  36. Optimum Effective Fanout f Optimum f for given process defined by g fopt = 3.6 forg=1 L'Inverter CMOS

  37. Normalized delay function of F L'Inverter CMOS

  38. Power Dissipation L'Inverter CMOS

  39. Where Does Power Go in CMOS? L'Inverter CMOS

  40. Dynamic Power Dissipation Vdd Vin Vout C L 2 Energy/transition = C * V L dd 2 Power = Energy/transition *f* dd Not a function of transistor sizes! Need to reduce C , V , and f to reduce power. L dd L'Inverter CMOS

  41. Modification for Circuits with Reduced Swing L'Inverter CMOS

  42. Node Transition Activity and Power L'Inverter CMOS

  43. Energy Delay Product PDP (Power Delay Product) = PavTp=CLVDD2/2 Energia per commutazione EDP = PDP x tp tp=αCLVDD/(VDD-VTe) dove VTe=VT+VDSAT/2 EDP = αCL2VDD3/2(VDD-VTe) VDDopt = 3/2VTe L'Inverter CMOS

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