CAE/CAD Tools

1. CAE/CAD Tools Marin Hristov Advanced level study programme in Electronics Design and Integration Technologies 28213-IC-1-2005-1-BE-ERASMUS-PROGUC-3 2006-2322 / 001-001 SO2 Technical University of Sofia Faculty of Electronics ECAD Laboratory 2008

2. CADENCE Design Framework

3. Cadence Design Framework II is a common interface to the complete range of Cadence IC design tools. Using a common database and user interface, the framework allows easy cross checking between the various stages of the design flow, e.g. comparing the layout and the schematic. The following describes the components of the Cadence Design Framework II which are used for digital design.

4. Cadence FLOW

5. Design Specifications Design Specification typically describe the expected functionality (Boolean operations) of the designed block, as well as the maximum allowable delay times, the silicon area and other properties such as power dissipation. Usually, the design specifications allow considerable freedom to the circuit designer on issues concerning the choice of a specific circuit topology, individual placement of the devices, the locations of input and output pins, and the overall aspect ratio (width-to-height ratio) of the final design. In a large-scale design, the initial design specifications may also evolve during the design process to accomodate other specs or limitations.

6. Design Specifications As an example, the initial design specs of a one-bit binary full adder circuit are listed below: • Technology: 0.8 um twin-well CMOS • Propagation delay of "sum" and "carry_out" signals < 1.2 ns (worst case) • Transition times of "sum" and "carry_out" signals <1.2 ns (worst case) • Circuit area < 1500 um^2 • Dynamic power dissipation (at VDD=5 V and fmax=20 MHz) < 1 mW

7. Schematic Capture The traditional method for capturing (i.e. describing) your transistor-level or gate-level design is via the schematic editor. Schematic editors provide simple, intuitive means to draw, to place and to connect individual components that make up your design. The resulting schematic drawing must accurately describe the main electrical properties of all components and their interconnections. Also included in the schematic are the power supply and ground connections, as well as all "pins" for the input and output signals of your circuit. This information is crucial for generating the corresponding netlist, which is used in later stages of the design. The generation of a complete circuit schematic is therefore the first important step of the design flow.

8. Schematic Capture • In order to setup your environment to run Cadence applications you need to open an xterm window and type • . cdscdk • this script modifies your environment (sets PATH and exports variables). To see your current environment type the following at the prompt: • set • Running the Cadence tools • Now you should be able to run the Cadence tools. Never run Cadence from your root directory, it creates many extra files that will clutter your root. Instead please create a directory (e.g. cadence) and start Cadence there by typing: • mkdir cadencecd cadenceicfb &

9. Schematic Capture The command icfb & starts Cadence in the background and you should get a window with the icfb Command Interpreter Window (CIW) as below: With the CIW you can launch other applications and you can also manage your files and libraries. For more information read here…

10. Schematic Capture In order to create new libraries go to File -> New -> Library from the File menu of the Library Manager. Then fill in the name of the new library (e.g. Tutorial) in the dialog window, and leave the Path empty. Click on Attach to existing tech library and choose AMI 060u C5N (#M, 2P, high-res) from all the options. Leave I/O Pad Type as Perimeter then click OK.

11. Schematic Capture Start by clicking on the Tutorial library in the Library Manager window once, then go to File -> New -> Cell View and fill in with IVcurves as the cell name, schematic as the view name, and Composer - Schematic as the tool, then press OK. You should get the Virtuoso Schematic Editing window. You also have access to these commands (and others) from the menu. For more information read here…

12. Schematic Capture Our first schematic will be used to plot IV curves. Click on the Instance button (which looks somewhat like an IC, or go to Add -> Instance), this will pop-up two small windows, one being a Component Browser window. In this window choose NCSU_Analog_Parts as the library, click on N_Transistors, then on nmos4 (an NMOS transistor with all 4 terminals, G, S, D, B):

13. Schematic Capture In Add Instance windowyou can place the 5 transistors by clicking on the left mouse button for the first transistor and then moving the mouse down and clicking again. Do that right now. If you make mistakes you can always go to Edit -> Undo and try again. You can press the ESC key on the keyboard to get out of the placeinstance mode or you can keep placing other parts.

14. Schematic Capture You can also move, delete parts, please explore the different editing functions, you will only learn by making mistakes and then correcting them. Now we also need to add ports, wires and power supply. First let's add ground by clicking on Instance again and then choosing Supply-Nets and then gnd in the component browser window, then place one gnd below the 5 transistors. For more How toEdit information read here…

15. Schematic Capture Then add wires (narrow) toconnect all transistor sources and bodies to the ground. Now add 6 DC voltage sources, one for VDS and one for each VGS and then connect them with wires to the transistors. Unfortunately we also need to add 5 more "dummy" voltage sources (with a value of 0 V) so that we can plot the currents in the transistors. The DC voltage sources that we are going to use are in the Voltage_Sources directory with the name vdc.

16. Schematic Capture Finally add the 5 dummy 0 V sources in series with the drains, and a voltage source vdc of 5 V for VDS. Press ESC to get out of the add instance mode. In case you made a mistake you can always go to Edit -> Undo, or you can correct your mistake by some form of edit. For more information about Edit Properties, read here…

17. Schematic Capture For example, if you filled in the wrong value for the DC voltage for vdc you can always change that later by first selecting the instance (click on it in the schematic) and then go to Edit -> Properties -> Objects, then a pop-up window will appear where you can change what you want.

19. SIMULATION After the description of a circuit is completed using the Schematic Editor, the electrical performance and the functionality of the circuit must be verified using a Simulation tool. The detailed transistor-level simulation of your design will be the first in-depth validation of its operation. Based on simulation results, the designer usually modifies some of the device properties in order to optimize the performance. The initial simulation phase also serves to detect some of the design errors that may have been created during the schematic entry step. It is quite common to discover errors such as a missing connection or an unintended crossing of two signals in the schematic.

20. Simulation For our first schema with 5 transistors in the Virtuoso Schematic window go to Tools -> Analog Environment. The design should be set to the right Library, Cell and View. First we need to choose the simulator , we will choose Spectre. Go to Setup -> Simulator/Directory/Host, and choose Spectre in the pop-up window, then click OK. For more information about Spectre, read here…

21. Simulation Now you need to choose the type of simulation, go to Analyses -> Choose... In this case we will choose a dc-sweep so click on the dc radio button, then on Component Parameter, then on Select Component (all of these in the Choosing Analyses dialog window) then on the VDS component in the schematic window and choose dc in the Select Component Parameter pop-up window and click OK.

22. Simulation After saving the file we can finally simulate! Click on the Netlist (more read here…) and Run button on the right or go to Simulation -> Netlist and Run. Click OK on the Welcome to Spectre window whichshould start the simulation: For more detailed information, read here…

23. Simulation Next step is to go to Results -> Direct Plot -> DC which will pop-up your schematic window. Now you have to click on the signals you want to see. Since this is a dc-sweep we want to see the drain currents into the 5 transistors. In order to do this you have to click on the small red square at + terminal of each of the dummy power supplies in series with each drain.

24. Simulation Make sure you click on the red square (the pin) which means current, versus any other part which means net, or voltage. Click on all 5 power supplies. If you are pressing right on the pins a circle should appear around each chosen pin.

25. Simulation Now press on the ESC key (to finish choosing the signals) and you should get the desired simulation results, 5 IV curves as in the textbook. For detailed information about Spectre, read here…

26. Hierarchical Schematic Capture If a certain circuit design consists of smaller hierarchical components (or modules), it is usually very beneficial to identify such modules early in the design process and to assign each such module a corresponding symbol (or icon) to represent that circuit module. This step largely simplifies the schematic representation of the overall system. A symbol view of the circuit is also required for some of the subsequent simulation steps, thus, the schematic capture of the circuit topology is usually followed by the creation of a symbol to represent the entire circuit. The shape of the icon to be used for the symbol may suggest the function of the module (e.g. logic gates - AND, OR, NAND, NOR), but the default symbol icon is a simple rectangular box with input and output pins. Note that this icon can now be used as the building block of another module, and so on, allowing the circuit designer to create a system-level design consisting of multiple hierarchy levels.

27. Hierarchical Schematic Capture In case you are going to use input, output and bidirectional ports(CMOS inverter), you can place these either by pressing the PIN button on the left or by going to Add -> Pin... First add one nmos4 transistor and one pmos4 transistor, a gnd and a vdd symbol (from the Supply_Nets directory in the NCSU_Analog_Parts library) and then an input port IN and and output port OUT. Formore information, read here…

28. Hierarchical Schematic Capture Now connect everything with wires as an inverter and change the transistor properties such that the ratio of pmos to nmos is the "rule of thumb = 2", i.e. make the pmos 3um in width. Don't forget to connect the transistor bodies to the proper voltages (gnd for nmos and vdd for pmos). Your final schematic should look like this:

29. Hierarchical Schematic Capture Now we can create a hierarchical schematic that uses the symbols that we just created. Go to the Library Manager and with the Tutorial library highlighted do File -> New -> Cell View and create a schematic view for a cell named InvRing. The Composer schematic editor window should open up. Let's create a schematic of a ring oscilator with 11 inverters. Click on instance and choose the symbol view of the cell inverter in the Tutorial library. We are going to place 6 inverters first and we can do that with just one command by filling the Array inputs, let's say Rows 1 and Columns 6 (all 6 inverters will be arranged horizontally).

30. Hierarchical Schematic Capture Now click once to place the left most inverter, then move the mouse to the right and click again to place the remaining ones.

31. Hierarchical Schematic Capture Now we only need to wire the 11 inverters into a ring and add a vdd and a gnd symbol from the NCSU_Analog_Parts -> Supply Nets library (leave them unconnected on the top).

32. Hierarchical Schematic Capture Many times when you have a complex hierarchical schematic you may want to make modifications on different cells without having to close and open different windows. You can do that by traversing the hierarchy. You can traverse both up and down, for example you can go down from the InvRing schematic and make modifications in the inverter schematic, then go back up the hierarchy. To do that you have to click on the symbol that you want to descend to (in the Virtuoso Schematic window), then go to Design -> Hierarchy -> Descend Edit, then click OK on the pop-up dialog box.

33. Hierarchical Schematic Capture Now we are going to create a hierarchical schematic at the logic (gate) level by using symbols for lower level schematics. When creating such a schematic it is sometimes necessary to use different gates with the same logic but with different transistor sizes (e.g. a "weak" inverter and a "strong" inverter). For these purposes it is good if the sizes of the transistors are parameterized. We will use the schematic and symbol for the inverter that we created earlier.

34. Hierarchical Schematic Capture Let's copy the existing inverter cell to 4 other cells, let's call them: Invx1, Invx4, Invx16 and Loadx64, respectively. These will be a parameterized inverter with minimum size (x1), 4 times the minimum (x4), 16 times the minimum (x16) a fix load 64 times the minimum. In order to copy the cells first click on the library, then on the inverter cell, then go to Edit -> Copy, and fill the new name of the cell in the To unfilled part, and make sure that Copy All Views is checked. In this way you should get 4 more cells in the Tutorial library.

35. Hierarchical Schematic Capture Open the schematic viewby double clicking on the schematic view in the Library Manager window. We now need to change the properties Width and Length for the transistors such that they are parameterized. Edit properties for the nmos and change Length to: Len and Width to: Wid, then pmos and change Length to: Len and Width to: a*Wid.

36. Hierarchical Schematic Capture When we use this inverter in a hierarchical schematic we can now keep the default values or change the default values to go to a different technology (e.g. change Len to 0.25u for a 0.25u CMOS technology) or have different transistor strengths for different inverters.

37. Hierarchical Schematic Capture Now change the sizes for Invx4, Invx16 and Loadx64. For all of them make the length Len, both for PMOS and NMOS. This is the standard practice for digital design where transistors are minimum length for high performance. Then make the widths: • a*b*Wid for PMOS, b*Wid for NMOS for Invx4 • a*b*b*Wid for PMOS, b*b*Wid for NMOS for Invx16 • a*c*Wid for PMOS, c*Wid for NMOS for Loadx64

38. Hierarchical Schematic Capture We should also edit the symbols of the 4 new cells to reflect their different characteristics. Let's do it though, go to the Library Manager and double click on the symbol view of the Invx1 cell. Go to Edit -> Properties -> Objects... and then clik on the text inv on the symbol itself. In the pop-up window fill Invx1 as the Label, then clik OK.

39. Hierarchical Schematic Capture Now let's assign sizes to the 4 inverters. We are interested in the inverter delay for a fanout of 4 and assume that an inverter 4 times larger than the base size is equivalent to 4 base inverters. This means that we can keep the first inverter at the base size, make the second one 4 times larger, the 3rd one 16 times larger and the 4th one 32 times larger, simply by making the parameter b = 4.

40. Hierarchical Schematic Capture The last skill in the schematic entry will be to traverse hierarchy. For this go to Design -> Hierarchy -> Descend Edit and then click on the first inverter and then clik OK. You should get to the inverter schematic where you can verify that the sizes are actually as you would expect.

41. Simulation Hierarchical Schema For Simulation we use two inverters for delay such that we can take both tpLH and tpHL into account without having to do manual addition. In the Composer window go to Tools -> Analog Environment. The design should be set to the right Library, Cell and View. We also need to set up inputs and power supply since we don't have explicit voltage sources. Go to Setup -> Stimuli.

42. Simulation Hierarchical Schema We need to setup both inputs (IN1) and the global sources (power supply). For IN1 use a pulse with amplitude 5 (Voltage 1=0, Voltage 2=5) with 0.4n rise and fall times and 1.6n pulse width and 4n period, make sure you enable it. Click on the Global Sources, you should have only one (vdd!). Click on Enabled, Function dc, Type Voltage, DC voltage 5, Source type dc, and click on Apply. Now you need to choose the type of simulation, go to Analyses -> Choose... In this case we will choose tran which is the default, 8n as the Stop time and moderate as the accuracy default. Save All. The only other settings that we need are the variables a, b, c, Len and Wid, for now let's set a=2, b=4, c=64, Len=0.6u, Wid=1.5u.

43. Simulation Hierarchical Schema The variable a should now appear in the Design Variables list. Do the same for b, c, Wid, Len. All variables should now appear in the Design Variables list.

44. Simulation Hierarchical Schema For the simulationclick on the Netlist and Run button on the right Click OK on the Welcome to Spectre window which should start the simulation. For simulation results go to Results -> Direct Plot -> Transient Signal which will pop-up your schematic window. Since this is a transient analysis we want to see a few voltages. In order to do this you have to click on the desired nets, then the ESC key. Click on OUT, IN1, IN2 and IN3.

45. Simulation Hierarchical Schema Now we can measure tpLH, tpHL for the second and third inverters (signals IN2 and IN3). To do this accurately we are going to use the waveform calculator. Go to Tools -> Calculator in the Analog Environment window which should pop up the calculator.

46. Simulation Hierarchical Schema Now do Analysis -> Start in the Parametric Analysis window. Once the simulations are over we can again plot the waveforms. Go to Results -> Direct Plot -> Transient Signal and then choose IN2 and OUT.

47. Simulation Hierarchical Schema The first observation that we can make is that the delays are quite close even if we changed the pmos/nmos ratio quite drastically (from 1 to 3), which should reinforce the idea that complementary static CMOS is non-ratioed. If we zoom on the HL transition you will discover that the fastest solution in this case is actually the a = 1 waveform where the pmos and nmos are equal (412ps vs. 468ps when a=2.8).

48. Simulation Hierarchical Schema On the other hand if you look at the LH transition you can see that the solution with a = 1 has a poor rise time while a = 1.4 or a = 1.6 have much better rise times and still have small delays. From this superficial analysis we can conclude that indeed a value around a = 1.5 (close to sqrt(2-3) = 1.41-1.73 as suggested in class) is close to optimal for delay and decent rise time.

49. Layout and DRC (Design Rule Checking) The creation of the mask layout is one of the most important steps in the full-custom design flow, where the designer describes the detailed geometries and the relative positioning of each mask layer to be used in actual fabrication, using a Layout Editor. The created mask layout must conform to a complex set of design rules, in order to ensure a lower probability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker, is used to detect any design rule violations during and after the mask layout design. The designer must perform DRC (in a large design, DRC is usually performed frequently - before the entire design is completed), and make sure that all layout errors are eventually removed from the mask layout, before the final design is saved.

50. Layout and DRC Now we are going to create a layout for our inverter schematic. We are going to use the SCMOS_SUBM scalable CMOS design rules for submicron processes available from MOSIS. The AMI C5N process uses LAMBDA = 0.3u which seems to be in contradiction with the claim that it is a 0.5u process. LAMBDA = 0.3u is really chosen for satisfying the design rules for everything but transistor length which with extra step is done at MOSIS to reduce it from the drawn 0.6u to 0.5u. Change the width of the nmos to 5 lambda and of the pmos to 10 lambda.