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LOGIC DESIGN

LOGIC DESIGN. M EDIUM S CALE I NTEGRATED CIRCUITS (MSI). Updated 5: November 2012. Ertuğrul Eriş. 1. EE33201 COURSE ASSESMENT MATRIX. 4-BIT PARALEL ADDER. BCD/EXCESS 3 CODE CONVENTOR . FULL ADDER. LOOK AHEAD CARRY ADDER-1. C 0 = input carry C 1 = G 0 + P 0 C 0

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LOGIC DESIGN

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  1. LOGIC DESIGN MEDIUM SCALE INTEGRATED CIRCUITS (MSI) Updated 5: November 2012 Ertuğrul Eriş Ertuğrul Eriş 1

  2. EE33201 COURSE ASSESMENT MATRIX

  3. 4-BIT PARALEL ADDER Ertuğrul Eriş

  4. BCD/EXCESS 3 CODE CONVENTOR Ertuğrul Eriş

  5. FULL ADDER Ertuğrul Eriş

  6. LOOK AHEAD CARRY ADDER-1 C0 = input carry C1 = G0 + P0 C0 C2 = G1 + P1C1 = G1 + P1 ( G0 + P0 C0 ) = G1 + P1 G0 + P1 P0 C0 C3 = G2 + P2 C2 = G2 + P2 G1+ P2 P1 G0 + P2 P1 P0 C0 Ertuğrul Eriş

  7. LOOK AHEAD CARRY ADDER-2 Pi = Ai Bi Gi = Ai . Bi Si = Pi Ci Ci+1 = Gi + Pi Ci Ertuğrul Eriş

  8. BINARY ADDER/SUBTRACTOR -B will be applied as 2’s complements How to generalized for n-bit? Ertuğrul Eriş

  9. BCD ADDER How to generalized for n-bit? binary and BCD adders comparison? Ertuğrul Eriş

  10. TWO BIT BINARY MULTIPLIER How to generalized for n-bit? Ertuğrul Eriş

  11. MULTIPLICATION OF 3 AND 4 BIT BINARY NUMBERS • Alternative algorithms? • pereted sum • shifting sum How to generalized for n-bit? Ertuğrul Eriş

  12. COMPARATOR Inputs: A = A3 A2 A1 A0 ve B = B3 B2 B1 B0 A < B için Ç1 = 1 Ç2 = 0 Ç3 = 0; A > B için Ç1 = 0 Ç2 = 1 Ç3 = 0; A = B iken Ç1 = 0 Ç2 = 0 Ç3 = 1 Xi = AiBi + A'iB'i i = 0,1,2,3 A = B → Ç3 = x3 x2 x1 x0 = 1 A > B → Ç2 = A3B‘3 + x3 A2B‘2 + x3 x2A1B‘1 + x3 x2 x1A0B‘0 A < B → Ç1 = A‘3B3 + x3 A‘2 B2 + x3 x2A‘1B 1 + x3 x2 x1A‘0B0 What happens if use calassical design? Would ir br enaugh to have two outputs? What could benefit of having three outputs? Why it has been avoided to have a comparator circuit for binary subtraction? Ertuğrul Eriş

  13. COMPARATOR Inputs: A=A3A2A1A0 ve B=B3B2B1B0 A < B için Ç1 = 1 Ç2 = 0 Ç3 = 0; A > B için Ç1 = 0 Ç2 = 1 Ç3 = 0; A = B iken Ç1 = 0 Ç2 = 0 Ç3 = 1 Xi = AiBi + A'iB'i i = 0,1,2,3 A=B Ç3 = x3 x2 x1 x0 = 1 A>B Ç2 = A3B‘3 + x3 A2B‘2 + x3 x2A1B‘1 + x3 x2 x1A0B‘0 A<B Ç1 = A‘3B3 + x3 A‘2 B2 + x3 x2A‘1B 1 + x3 x2 x1A‘0B0 Ertuğrul Eriş

  14. DECODERS3X8 What are the outputs if you think canonical forms? Ertuğrul Eriş

  15. DECODERS-2(2X4 WITH ENABLE INPUT) Active (0) output 0 Ertuğrul Eriş

  16. CAPACITY INCREASE FOR DECODERS(Two 3X8 → One 4X16 ) • Interpretation of Enable input? • work/no work • capacity increase Ertuğrul Eriş

  17. FUNCTION REALIZATION BY USING DECODERS/FULL ADDER C=Σ3,5,6,7 S=Σ1,2,4,7 Two function one decoder, multiple function generalization? Decoder: software → Hardware control Ertuğrul Eriş

  18. ENCODER (8 bit) Wiil be performed as an Experipent in LAB Observe the output, say the input!!. X = D4+D5+D6+D7 Y = D2+D3+D6+D7 Z = D1+D3+D5+D7 Observe the output, say the input, not true for 0 output? What could be solution? If more than one input (1) than output confusing for exampla 3 and 6 output 7? solution Priorty encoder. Where do we need Encoder function on PC? Ertuğrul Eriş

  19. FUNCTION REALIZATION BY USING DECODERS/ENCODER • ENCODER DESIGN BY USING DECODER(S)? • GENERALIZE DECODER USAGE FOR FUNCTIONS REALIZATIONS • Benefits • When preferable • Compare this realizations with SSI realizations Ertuğrul Eriş

  20. MSI PRIORITY ENCODER (4 bit) V output: differentiate D0D1D2D3 (0000) input from others. X and y outputs determine inputs D0 D1D2D3 (1) values with piorty. Previous endoceder was 8-bit, this one is 4-bit with piority. 1 Error in Mano: for 1010 input output should be (1) not (x). Ertuğrul Eriş

  21. DECODER/DEMUX WITH ENABLE INPUT 1X4 – demux, what could be the use? Switching! E input values are transfered to different outputs under the control of x1 and x2 input values! Ertuğrul Eriş

  22. 2X1 MULTIPLEXER (MUX) Same component two different interpretations: mux: Leading the data coming from two different sources to the same destination under the control of s input. mux: implementation of four one-variable functions. • Multiplexing/deMultiplexing • Audio (Telefon,ses)data communication: source+transmisson line (media)+destination • communication within the same system: source+ BUS+destinaton Ertuğrul Eriş

  23. 4X1-MULTIPLEXER (MUX) Interpretation1:Transferring the data in any order from four different sources to the same line by the control of S0 and S1 inputs. Interpretation2: Realization of 8 two-variable-functions. Ertuğrul Eriş

  24. FUNCTION REALISATION BY USING MUX’s Interpretation1: Addional one NOT gate is required for the realization of three-variable functions by usiang a 4x1 mux. Interpretation2 : What is the benefits of using mux’s in function realization? Ertuğrul Eriş

  25. FUNCTION REALISATION BY USING MUX’s Interpretation1: Addional one NOT gate is required for the realization of four-variable functions by usiang a 8x1 mux. Interpretation2 : What is the benefits of using mux’s in function realization? Ertuğrul Eriş

  26. FUNCTION REALISATION BY USING MUX’s • GENERALIZE MUX USAGE FOR FUNCTION REALIZATIONS • Independent variables and mux capacity relation • Low capacity mux usage for high number of independent variables • WHEN PREFERABLE?WHY? • What are function realizations being examined up now? Any more? How? Ertuğrul Eriş

  27. TRUTH TABLE VS FUNCTION TABLE • SSI ELEMANTS TRUTH TABLE • MSI ELEMENTS TRUTH TABLE NOT PRACTICAL • MSI ELEMENTS DEFINITION BY FUNCTION TABLES • COMPARE TRUTH AND FUNCTION TABLES Ertuğrul Eriş

  28. MUX AS A MULTIPLEXER Quadruple two-to-one-line multiplexer Two-to-one multiplexer A: data source1 B: data source 2 Y: data lines(BUS) E,S:Kontrol inputs BUS capacity, number of sources, size of data is known, determine mux capacity(size)? Ertuğrul Eriş

  29. COMMUNICATION:PARALEL DATA (4 bits) TRANSFER(SWITCHING) BY MUX/DECODER Sources: A and B, Data/Bus: four bits, Destinations: C,D Decoder enable Mux output DM3 1X2 DM1 1X2 DM2 1X2 C2 D2 C1 D1 C0 D0 A1 B1 A3 B3 A0 B0 A2 B2 M1 2X1 DM4 1X2 C3 D3 M2 2X1 M4 2X1 M3 2X1 Data select Data select 1X2 Demux=2X1 Decoder with enable What should be mux /decoder sizes in order to transfer 8-bit data from four different sources to four different destinations? Ertuğrul Eriş

  30. COMMUNICATION:SERIAL DATA (2 bits) TRANSFER(SWITCHING) BY MUX/DECODER Sources: X, Y,Z,W Data/Bus: One, Destinations: A,B,C,D,E,F,G,H A DM 1X8 OR DECODER 3X8 X Y M 4X1 B C Decoder enable Mux output D Z W E F G Data select H What should be data select input in order transfer X data to H destination? Data select Ifwedidn’thavesuch a systemforcommunicationwhatwould be solution? OR What is thebenefit of such a switchingsystem? Ertuğrul Eriş

  31. PROGRAM DESIGN DEPT, PROGRAM G R A D U A T E S T U D E N T STUDENT P R OG R A M O U T C O M E S PROGRAM OUTCOMES P R OG R A M O U T C O M E S STATE, ENTREPRENEUR FIELD QALIFICATIONS EU/NATIONAL QUALIFICATIONS KNOWLEDGE SKILLS COMPETENCES NEWCOMERSTUDENT ORIENTIATION GOVERNANCE Std. questionnaire ALUMNI, PARENTS ORIENTIATION STUDENT PROFILE Std. questionnaire FACULTY NGO STUDENT, ??? CIRCICULUM ??? INTRERNAL CONSTITUENT Std. questionnaire EXTRERNAL CONSTITUENT EXTRERNAL CONSTITUENT REQUIREMENTS EU/NATIONAL FIELD QUALIFICATIONS PROGRAM OUTCOMES QUESTIONNAIRES QUALITY IMP. TOOLS GOAL: NATIONAL/INTERNATIONAL ACCREDITION

  32. BLOOM’S TAXONOMYANDERSON AND KRATHWOHL (2001) !!Listening !! Doesn’t exits in the original!!! http://www.learningandteaching.info/learning/bloomtax.htm Ertuğrul Eriş

  33. ULUSAL LİSANS YETERLİLİKLER ÇERÇEVESİ BLOOMS TAXONOMY Ertuğrul Eriş

  34. COURSE ASSESMENT MATRIX LEARNING OUTCOMES Ertuğrul Eriş

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