1. DELHI TECHNOLOGICAL UNIVERSITY (Formerly Delhi College of Engineering) Bawana Road, Delhi-110042 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING VLSI DESIGN EC-302 PROJECT REPORT: 7T SRAM Submitted to: Submitted by: Prof. Neeta Pandey Anish Kumar Biswal (2K21/EC/29) Anshika (2K21/EC/38)

2. CANDIDATE’S DECLARATION We, Anish Kumar Biswal (2K21/EC/29) and Anshika (2K21/EC/38), students of B.Tech in Electronics and Communication Engineering, hereby declare that the Project Dissertation titled "7T SRAM" submitted by us to the Department of Electronics and Communication Engineering, DTU, Delhi, in fulfillment of the requirement for awarding the Bachelor of Technology degree, is not copied from any source without proper citation. This work has not previously formed the basis for the award of any Degree, Diploma, Fellowship, or other similar title or recognition. Place: New Delhi Anish Kumar Biswal (2K21/EC/29) Date: 23/04/2024 Anshika (2K21/EC/38)

3. CERTIFICATE I hereby certify that the Project titled "7T SRAM" submitted by Anish Kumar Biswal (2K21/EC/29) and Anshika (2K21/EC/38) for fulfillment of the requirements for the awarding of the degree of Bachelor of Technology (B.Tech) is a record of the project work carried out by the students under my guidance and supervision. To the best of my knowledge, this work has not been submitted in any part or fulfillment for any Degree or Diploma to this University or elsewhere. Place: New Delhi Date: 23/04/2024 Prof. Neeta Pandey Department of Electronics and Communication Engineering Delhi Technological University

4. ACKNOWLEDGEMENT We extend our heartfelt gratitude to Prof. Neeta Pandey, of the Department of Electronics and Communication Engineering, Delhi Technological University, and all other faculty members of our department for their constant guidance, motivation, and support throughout this project. We are deeply indebted to our supervisor, Prof. Neeta Pandey, for her invaluable assistance, encouragement, and expertise, which have been instrumental in the successful completion of this project. We also acknowledge the support and guidance received from various sources, directly or indirectly, which have contributed to the realization of this project. Lastly, we express our sincere thanks to our well-wishers and parents for their unwavering support and encouragement. Anish Kumar Biswal (2K21/EC/29) Anshika (2K21/EC/38)

5. ABSTRACT This project presents the design and analysis of a 7T SRAM (Static Random Access Memory) cell tailored for high-performance applications. SRAM cells are fundamental building blocks in modern integrated circuits, crucial for fast data storage and retrieval. The proposed 7T SRAM cell aims to address the challenges posed by technology scaling, such as increased leakage currents and reduced noise margins, while maintaining high performance and reliability. The cell architecture employs a combination of pass transistors and access transistors to achieve read and write operations efficiently. Moreover, the 7T configuration offers improved stability against process variations and reduced susceptibility to soft errors compared to conventional 6T SRAM cells. In this study, comprehensive simulations are conducted to evaluate the performance metrics of the proposed 7T SRAM cell, including read and write access times, static noise margins, power consumption, and stability. The results demonstrate that the 7T SRAM cell achieves competitive performance metrics compared to existing SRAM cell designs, making it a promising candidate for high-performance applications in advanced technology nodes. Furthermore, the insights gained from this analysis provide valuable guidelines for future SRAM cell designs aimed at meeting the increasing demands of next-generation integrated circuits.

6. CONTENTS  Introduction  Background and Motivation  7T SRAM Cell Scheme  Cell Design Consideration  Architecture and Operation of 7T SRAM  Comparison with conventional 6T SRAM  Simulations and Waveforms  Conclusion  References

7. INTRODUCTION SRAM is still a crucial component of system-on-a-chips (SoCs). For on-chip SRAMs, the low-power characteristic is becoming more crucial, particularly for battery-powered portable applications. It is, therefore, also one of the biggest obstacles facing high-speed VLSI circuits, whose main goal is great performance rather than low power. Bit widths of 16 to 256 or more are common in on-chip SRAMs, and this trend continues as systems get more complicated in an effort to achieve higher performance. Because these SRAMs are full swing during write cycles, the highly capacitive bit/data lines are primarily responsible for dissipating the active power of the SRAM. As a result, write cycles use a lot more power than read cycles do. The power estimation of 4-Mb SRAMs with two distinct structures is displayed in Fig. 1(b). Driving bit/data lines uses only 28% of the total power when the bit width is 8. However, this value increases to 90% when bit width increases to 256. One efficient method of lowering the power dissipation in write cycles is to reduce the voltage swing on the bitlines. By limiting the bitline swing to half while combining charge recycling, a 60% power saving was attained in the half-swing (HS) scheme [2]. However, write-error issues in the HS scheme make it challenging to lower the power further. Stable read operation is another issue with the HS system since precharging bitlines during a read cycle raises the risk of a cell data flip gone wrong. In actuality, half-precharging of bitlines has not been extensively employed in SRAMs, in contrast to DRAMs. Precharging in read cycles must therefore be avoided. Another problem arises if the bitline voltage level in read cycles is raised from half-in the HS method. The disparity between the bitline voltage levels in read and write cycles results in extra power consumption for bitline voltage recovery when the write and read cycles occur alternately.

8. BACKGROUND AND MOTIVATION The field of digital integrated circuits relies heavily on Static RandomAccess Memory (SRAM) for its fast and volatile memory requirements. Traditional SRAM cells, typically based on 6-transistor (6T) architectures, have been the cornerstone of memory design for decades. However, as the demand for low-power and high-performance computing continues to rise, the limitations of conventional 6T SRAM cells have become increasingly apparent. The motivation behind exploring alternative SRAM cell designs, such as the 7-transistor (7T) SRAM cell, stems from the need to address these limitations. While 6T SRAM cells offer fast access times and high density, they suffer from issues like high leakage current and susceptibility to process variations. The additional transistor in the 7T SRAM cell architecture presents an opportunity to mitigate these issues and potentially improve overall performance and efficiency. By exploring the background of SRAM technology and the motivations behind investigating 7T SRAM cells, this project aims to contribute to the ongoing efforts in advancing memory design for modern digital systems. Through comprehensive analysis and evaluation, we seek to identify the advantages and challenges associated with 7T SRAM cells and pave the way for their integration into future digital circuits.

9. 7T SRAM Cell Scheme Figs show the circuit diagram and the operation waveform of the proposed cell scheme, respectively. The salient feature of the scheme is an additional nMOS connected to the source of driver nMOS transistors of the memory cell, which enables small swing of bit lines in a write operation. This additional nMOS is referred as the switch Vss in the rest of this paper. A bit line is precharged to Vdd - Vtn by an nMOS load transistor and is pulled down to Vdd – Vtn -DBL in a write “0” operation, where Vtn and DBL are threshold voltage of the load nMOS and write swing, respectively. The precharge level must not be Vdd because access transistors of the cell cannot turn on in the write operation in this scheme. There is no additional power consumption even if the write and read cycles come alternately, because there is no mismatch between the voltage level of bit lines in read cycles and that in write cycles. The source-line control signal, SLC, is synchronized with the word line signal WL, and the switch Vss is turned off before WL goes up to high in a write cycle. Even if the voltage difference between a pair of bit lines is small, the cell node can be inverted because the driver nMOS transistors do not draw current while the word line is activated, thanks to the switch. After WL goes to low, SLC goes back to high and small-swing data is amplified to full swing inside a cell. Note that all the cells connected to the activated wordline should be written in a write cycle in this scheme. If the numbers of cells connected to a wordline and to an SLC signal line are 64 and 256, respectively, for example, data stored in 192 cells become unstable while 64 cells are written.

10. Cell Design Consideration In the proposed scheme, the primary concern in cell design is tradeoffs among read delay, noise margin, and cell area. Before going into quantative analysis of these three issues, it is explained that the tradeoffs are tightly related to two design parameters of the switch Vss: b and N Fig.5 shows the equivalent circuit of a proposed cell in a read cycle. Along the read current path, there are three nMOS transistors stacked. They are a cell access transistor, a cell driver transistor, and the switch Vss, whose width are denoted as Wa, Wd and Wsw, respectively. By defining b as the ratio of Wsw to Wd , the first key design parameter b is obtained. With such a definition, b becomes independent of technology-specific parameters and the following discussions can be applied to every technology node. In a conventional six-transistor cell, Wd is set around 3Wa and b is virtually infinite. According to the insertion of the switch Vss having finite value, read current and static noise margin will decrease. Therefore, it is clear that larger is better in terms of read delay and noise margin, but its maximum value is strictly limited by area constraints. The second key parameter N, is related to a layout issue of the switch Vss. The switch cannot be placed cell by cell because area overhead goes beyond 20%. Therefore, it should be shared by a group of neighbouring cells. In this case, there are three elements in each row which cause area penalty. They are the SLC signal line, the switch itself, and the common source line which connects each cell to the switch.. The simplest way is to set the value of to its maximum, the same as the bit width. Such a configuration is, however, impossible in practice, due to the following reason. Fig. 5 shows the read current path in the shared switch structure. When read current flows through each cell in read cycles, the maximum current through the common source line is as large as N. IR

11. ARCHITECTURE AND OPERATION OF 7T SRAM The architecture and operation of a 7T SRAM cell involve detailed examination of its circuitry and functionality. In this specific SRAM cell design, an additional transistor is introduced compared to the traditional 6-transistor (6T) SRAM cell. This additional transistor enhances the stability and reliability of the cell. The architecture of the 7T SRAM cell typically consists of seven transistors arranged in a specific configuration. These transistors are interconnected in such a way that they allow for the storage of a single binary bit of information. In the operation of a 7T SRAM cell, the primary components involved are the wordline (WL), bitline (BL), and its complementary bitline (/BL). These elements orchestrate the essential functions of writing and reading data within the SRAM cell. During the writing process, the wordline plays a pivotal role as it serves as the control signal to activate the targeted SRAM cell. When a specific address is provided, the corresponding wordline is activated, allowing access to the cell. Simultaneously, the bitline (BL) and its complementary bitline (/BL) are utilized for writing data into the cell. To write a '0' into the cell, for instance, the BL is driven to a low voltage level while the /BL remains high. Conversely, to write a '1', the BL is set high while the /BL is pulled low. This voltage differential between BL and /BL determines the state of the cell during the write operation. For reading data, the process involves activating the wordline to enable access to the targeted SRAM cell, similar to the writing operation. The stored data within the cell influences the voltage levels on the BL and /BL lines. These voltage levels are then sensed by a sense amplifier. Depending on the relative voltage levels between BL and /BL, the sense amplifier determines the stored data state, whether it is a '0' or a '1'. In summary, the operation of a 7T SRAM cell heavily relies on controlling the wordline and observing the voltage levels on the bitline and its complementary bitline pair. These components work together seamlessly to enable efficient data storage and retrieval within the SRAM cell, making it a crucial element in modern integrated circuits for high-performance applications.

12. COMPARISION WITH CONVENTIONAL 6T RAM Comparing the 7T SRAM cell with the conventional 6T SRAM cell provides a comprehensive understanding of their respective trade-offs and suitability for different applications. The 7T SRAM cell's additional pass transistor enhances its ability to isolate storage nodes from bitlines during read and write operations, leading to improved stability and reduced susceptibility to disturbances. This advantage comes at the cost of increased complexity, resulting in slightly slower access times and higher power consumption compared to the 6T SRAM cell. In contrast, the 6T SRAM cell's simpler structure offers faster access times and lower power consumption, making it well-suited for applications prioritizing speed and energy efficiency. However, the 6T SRAM cell's reliance on a single-ended bitline configuration renders it more vulnerable to noise and process variations, potentially limiting its performance in high-density and high-reliability applications. Despite occupying slightly more chip area due to its additional transistor, the 7T SRAM cell's benefits in terms of stability and reliability make it a preferred choice for demanding applications such as cache memories in high-performance computing systems, where data integrity and robustness are critical. Conversely, the 6T SRAM cell remains a popular choice for low-power and area-constrained applications, such as IoT devices and mobile electronics, where minimizing energy consumption and chip footprint are primary concerns. In summary, the choice between the 7T and 6T SRAM cells depends on the specific requirements of the target application, balancing considerations of speed, power efficiency, area utilization, and reliability.

13. Simulation and Waveforms

14. Conclusion Two main advantages are avoidance of half- precharging of bitlines and negative voltage on cell source lines. With these advantages, the proposed scheme can save more write power without degrading cell stability and device reliability. The possibility of reducing cell leakage power during active mode by slightly modifying the 7T cell scheme has also been explored.

15. References •Low Power 7T SRAM Cell Scheme - ''Saving Write Zero Power''By Anita Kumari and J.N.Roy University Centre for Instrumentation & Microelectronics, India •K. Mehrabi, B. Ebrahimi and A. Afzali-Kusha, "A robust and low power 7T SRAM cell design," 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS), Tehran, Iran, 2015, pp. 1-6, doi: 10.1109/CADS.2015.7377782. •Improved reliability single loop single feed 7T SRAM cell for biomedical applications Author links open overlay panel Ashish Panchal a, Priyanka Sharma b, Aastha Gupta b, Vaibhav Neema b, Nidhi Tiwari a, Ravi Sindal b