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qatar.cmu/~nabughaz/15447-f09/

CS-447– Computer Architecture Lecture 7 Instruction Set Architecture part II: addressing modes. www.qatar.cmu.edu/~nabughaz/15447-f09/. Last Time. Memory structures Address vs. data bus; use of decoder We looked at basic ISA design Mostly through examples

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qatar.cmu/~nabughaz/15447-f09/

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  1. CS-447– Computer Architecture Lecture 7Instruction Set Architecturepart II: addressing modes www.qatar.cmu.edu/~nabughaz/15447-f09/

  2. Last Time • Memory structures • Address vs. data bus; use of decoder • We looked at basic ISA design • Mostly through examples • Fixed or variable width instructions • Prefer fixed • Instruction must encode: • Opcode • What instructions should we support? • Operands • How many? Registers or memory? • addressing modes (today)

  3. The Stored Program Concept All instructions are represented by bits. All data are represented by bits. Implication: We can’t tell data apart from instructions Both instructions and data are stored in memory. Programs can operate on other programs. 3

  4. ISA Design Principles “The natural number of operands for an operation like addition is three…requiring every instruction to have exactly three operands, no more and no less, conforms to the philosophy of keeping the hardware simple” … Principle 1: Simplicity favors regularity. Simpler implementation Higher performance at lower cost RISC philosophy 4

  5. But… What if I want to add more than 2 numbers together? Such as: a = b + c + d + e Guess we can’t do that… Can we? 5

  6. But… can’t we make a 5 operand ADD? We could, but it would violate our simplicity principles. Parsing isn’t fun in software, it isn’t any more fun in hardware. if(opcode == OP_ARITHMETIC) { cin >> dest >> src1 >> src2; } Is nice, simple, clean, code. We don’t have to solve for any special cases if all arithmetic operations take 3 operands (and the first is the destination) 6

  7. Operands The operands to our instructions must be registers (we’ll talk about explicit values later). We are provided a 32 x 32-bit register file Used as the working set for the processor Small, fast, indexed from [0,31] Defines “word” as 32-bits. This is small! Not a lot to work with? Why? Design Principle 2: Smaller is faster 7

  8. Registers vs Memory Since 1975, all machines use general purpose registers Why? Faster than memory Easier for a compiler to use Temporary variable storage reduces memory pressure. Less loads and stores. Registers are easier to address than memory. Compilers have a lot of work to use registers effectively! 8

  9. How do we access memory? Consider: g = h + a[8]; g is in r1, h is in r2, a is in r3 (base address) First, remember that memory is byte-addressed. What is our offset to the array “a”? Now, we need to load that data. lw r4, 32(r3) # load word at r3 + 32 into r4 Then we can add as normal: add r1, r2, r4 9

  10. New Addressing mode! Notice that Load (store as well but not shown) looks different. Scary? lw r4, 32(r3) # load word at $s3 + 32 into $t0 add r1, r2, r4 Base address + offset determines the memory location. We just introduced a new addressing mode What addressing modes should we include in our ISA? What factors should determine that? 10

  11. Common Cases Small constants are quite common. Zero, in particular, is very common Because of this, some ISA’s such as MIPS define register $zero as always having the value of “zero”. This has other uses as well. MIPS doesn’t have “mov”, we replicate the behavior add $r2, $r1, $zero 11

  12. Allocation of Bits • Number of addressing modes • Number of operands • Register versus memory • Number of registers • Address range • Address granularity

  13. Addressing Modes • Immediate • Direct • Indirect • Register • Register Indirect • Displacement (Indexed) • Stack

  14. Immediate Operands An immediate operand is a value rather than a register. addi r3, r3, 4 # r3 += 4 This constant has to fit within the space remaining (after opcode, and two registers) within the instruction. Lucky for us, most constants are small! This is the common case, and leads us to… Design Principle 3: Make the common case fast. Avoid loading immediates from memory. 14

  15. Immediate Addressing • Operand is part of instruction • The address field points to the operand • e.g. ADD 525 • Add 525 to contents of accumulator • 525 is the operand • No memory reference to fetch data • Fast • Limited range

  16. Immediate Addressing Diagram Instruction OpCode Operand Example: ADD 525 ; AC = AC + 525 In an Accumulator-Based machine, we would like to add 525 to the accumulator, the result will be stored in the accumulator itself.

  17. Direct Addressing • Address field contains address of operand • Effective address (EA) = address field A • e.g. ADD A • Look in memory at address A for operand • Add contents of (A) to accumulator

  18. Direct Addressing (cont’d) • Single memory reference to access data • No additional calculations to work out effective address • Limited address space

  19. Direct Addressing Diagram Instruction Memory OpCode Operand Operand Example: ADD (Addr2) ; AC = AC + (2) ; (2) = 255

  20. Indirect Addressing (1) • Memory cell pointed to by address field contains the address of (pointer to) the operand • EA = (A) • Look in A, find address (A) and look there for operand • e.g. ADD (A) • Add contents of cell pointed to by contents of A to accumulator

  21. Indirect Addressing (2) • Large address space • 2n where n = address word length • May be nested, multilevel, cascaded • e.g. EA = ((A)) • Draw the diagram yourself • Multiple memory accesses to find operand • Hence slower

  22. Indirect Addressing Diagram Instruction Memory OpCode Operand Pointer to Operand ADD ((1)); AC = AC + ((1)) ((1)) = (3) = 255 = operand Operand Memory

  23. Register Addressing (1) • Operand is held in register named in address field • EA = R • Limited number of registers • Very small address field needed • Shorter instructions • Faster instruction fetch

  24. Register Addressing (2) • No memory access • Very fast execution • Very limited address space • Multiple registers helps performance • Requires good assembly programming or compiler writing • C programming: • register int a;

  25. Register Addressing Diagram Registers Instruction OpCode Operand Operand ADD R3 ; AC = AC + R3 ; AC = AC + 255

  26. Register Indirect Addressing • Similar to indirect addressing • EA = (R) • Operand is in memory cell pointed to by contents of register R • Large address space (2n) • One fewer memory access than indirect addressing

  27. Register Indirect Addressing Diagram Instruction Memory OpCode Operand Registers Operand Pointer to Operand Example:ADD (R3) ; AC = AC + (R3) = AC + (1) ; AC = AC + 255

  28. Displacement Addressing • EA = A + (R) • Address field hold two values • A = base value • R = register that holds displacement • or vice versa

  29. Displacement Addressing Diagram Instruction Memory OpCode Register R Address A Operand Registers Pointer to Operand + ADD (R2, BaseAddress) ; AC = AC + ; (R2+BaseAddress) ; AC = AC + (1) = AC + 255

  30. PC-Relative Addressing • A version of displacement addressing • R = Program counter, PC • EA = A + (PC) • i.e. get operand from A cells from current location pointed to by PC

  31. More on Branches Most branch targets are near the branch. They use an immediate value which acts as an offset based on the instruction immediately following the branch (PC+4). If the target is too far away, the assembler will rewrite the code. 31

  32. Base-Register Addressing • A holds displacement • R holds pointer to base address • R may be explicit or implicit

  33. Indexed Addressing • A = base • R = displacement • EA = A + R • Good for accessing arrays • EA = A + R • R++

  34. Combinations • Postindex • EA = (A) + (R) • Preindex • EA = (A+(R)) • (Draw the diagrams)

  35. Stack Addressing • Operand is (implicitly) on top of stack • e.g. • ADD Pop top two items from stack and add

  36. Example: MIPS Addressing Modes 36

  37. Memory Organization Design Question: Our registers are 32-bits. Byte-addressing points to an 8-bit chunk of data. How should we organize data? Since our working size is 32-bits, we should word-align our data. Why? 0 1 2 3 Aligned Not Aligned 37

  38. Endian Big Endian: Most significant byte is at the address of the word. IBM 360/370, Motorola 68K, MIPS, Sparc, HP PA Little Endian: Least significant byte is at the address of the word Intel 80x86, Dec Vax, Dec Alpha little endian byte 0 3 2 1 0 0 1 2 3 big endian byte 0 38

  39. An Example ISA – IA32

  40. %eax %edx %ecx %ebx %esi %edi %esp %ebp Moving Data: IA32 • Moving Data movlSource,Dest: • Move 4-byte (“long”) word • Lots of these in typical code • Operand Types • Immediate: Constant integer data • Like C constant, but prefixed with ‘$’ • E.g., $0x400, $-533 • Encoded with 1, 2, or 4 bytes • Register: One of 8 integer registers • But %esp and %ebp reserved for special use • Others have special uses for particular instructions • Memory: 4 consecutive bytes of memory • Various “address modes”

  41. movl $0x4,%eax temp = 0x4; movl $-147,(%eax) *p = -147; movl %eax,%edx temp2 = temp1; movl %eax,(%edx) *p = temp; movl (%eax),%edx temp = *p; movl Operand Combinations • Cannot do memory-memory transfer with a single instruction Source Dest Src,Dest C Analog Reg Imm Mem Reg movl Reg Mem Mem Reg

  42. Simple Addressing Modes • Normal (R) Mem[Reg[R]] • Register R specifies memory addressmovl (%ecx),%eax • Displacement D(R) Mem[Reg[R]+D] • Register R specifies start of memory region • Constant displacement D specifies offsetmovl 8(%ebp),%edx

  43. Indexed Addressing Modes • Most General Form • D(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]+ D] • D: Constant “displacement” 1, 2, or 4 bytes • Rb: Base register: Any of 8 integer registers • Ri: Index register: Any, except for %esp • Unlikely you’d use %ebp, either • S: Scale: 1, 2, 4, or 8 • Special Cases • (Rb,Ri) Mem[Reg[Rb]+Reg[Ri]] • D(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]+D] • (Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]]

  44. Address Computation Examples %edx 0xf000 %ecx 0x100

  45. Some Arithmetic Operations Format Computation • Two Operand Instructions addl Src,DestDest = Dest + Src subl Src,DestDest = Dest - Src imullSrc,DestDest = Dest * Src sall Src,DestDest = Dest << Src Also called shll sarl Src,DestDest = Dest >> Src Arithmetic shrl Src,DestDest = Dest >> Src Logical xorl Src,DestDest = Dest ^ Src andl Src,DestDest = Dest & Src orl Src,DestDest = Dest | Src

  46. Some Arithmetic Operations Format Computation • One Operand Instructions inclDestDest = Dest + 1 declDestDest = Dest - 1 neglDestDest = - Dest notlDestDest = ~ Dest

  47. Typical Operation Mixes – relatively stable since 1960. Load (from memory) Store (to memory) memory-to-memory move register-to-register move input (from I/O device) output (to I/O device) push, pop (to/from stack) Integer or FP Add, Subtract, Multiply, Divide shift left/right, rotate left/right not, and, or, set, clear unconditional, conditional call, return trap, return test & set (atomic r-m-w) search, translate parallel subword ops (4 16bit add) Data Manipulation Arithmetic Shift Logical Control – Jump/Branch Subroutine Linkage Interrupt Synchronization String Graphics (MMX) 49

  48. OF ZF SF Another Example ISA, Y86 Program registers Condition codes • Program Registers • Same 8 as with IA32. Each 32 bits • Condition Codes • Single-bit flags set by arithmetic or logical instructions • OF: Overflow ZF: Zero SF:Negative • Program Counter • Indicates address of instruction • Memory • Byte-addressable storage array • Words stored in little-endian byte order Memory %eax %esi %ecx %edi PC %edx %esp %ebx %ebp

  49. Y86 Instructions • Format • 1--6 bytes of information read from memory • Can determine instruction length from first byte • Not as many instruction types, and simpler encoding than with IA32 • Each accesses and modifies some part(s) of the program state

  50. %eax 0 %esi 6 %ecx 1 %edi 7 %edx 2 %esp 4 %ebx 3 %ebp 5 Encoding Registers • Each register has 4-bit ID • Same encoding as in IA32 • Register ID 8 indicates “no register” • Will use this in our hardware design in multiple places

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