Manufacturing-Aware Physical Design Andrew B. Kahng Puneet Gupta (Univ. of Calif. San Diego)
Outline • Challenges • “DFM Philosophy” • Manufacturing and Variability Primer • Design for Value • Composability • Performance Impact Limited Fill Insertion • Function Aware OPC • Systematic Variation Aware STA • Futures of Mfg-Aware PD
Layout 0.25µ 0.18µ 0.13µ 90-nm 65-nm Printing Figures courtesy Synopsys Inc.
Data Volume Explosion Number of design rules per process node MEBES file size for one critical layer vs. technology node
70% RET Layers Explosion Number of TSMC Mask Layers Using OPC/PSM Number of design rules per process node 0% 180nm 150nm 130nm 90 nm Source: TSMC Technology Symposium, April 22 2003
Design Rules Explosion Number of design rules per process node
Variation: Leakage • Subthreshold leakage current varies exponentially with threshold voltage: I exp(-Vth) • Vth = f(channel length, oxide thickness, doping) • Most affected by variations in gate length ±100% Isub ±10% Ld Dennis Sylvester, U. Michigan
Outline • Challenges • “DFM Philosophy” • Manufacturing and Variability Primer • Design for Value • Composability: PSM and Assists • Performance Impact Limited Fill Insertion • Function Aware OPC • Systematic Variation Aware STA • Futures of Mfg-Aware PD
Symptoms: Routing Rules (1) • Minimum area rules and via stacking • Stacking vias through multiple layers can cause minimum area violations (alignment tolerances, etc.) • Via cells can be created that have more metal than minimum via overlap (used for intermediate layers in stacked vias) • Multiple-cut vias • Use multiple-cut vias cells to increase yield and reliability • Can be required for wires of certain widths • Multiple via cut patterns have different spacing rules • Four cuts in quadrilateral; five cuts in cross; six cuts in 2x3 array; … • With wide-wire spacing rules, complicates pin access • Cut-to-cut spacing rules check both cut-to-cut and metal-to-metal when considering via-to-via spacing
Symptoms: Routing Rules (2) • Width- and Length-dependent spacing rules • Width-dependent rules: domino effects • Variant: “parallel-run rule” (longer parallel runs more spacing) • Measuring length and width: halo rules affect computation • Influence rules or stub rules • A fat wire, e.g., power/ground net, will influence the spacing rule within its surroundings any wire that is X um away from the fat wire needs to be at least Y um away from any other geometry. • Example: fat wire with thin tributaries • bigger spacing around every wire within certain distance of the thin tributaries • ECO insertion of a tributary causes complications • Strange jogs and spreading when wires enter an influenced area
Symptoms: Routing Rules (3) • Density • Grounded metal fills (dummy fill*) • Via isodensity rules and via farm rules (via layers must be filled and slotted, have width-dependent spacing rule analogs, etc.) • Non-rectilinear (-geometry) routing • X-Architecture: http://www.xinitiative.org/ • Y-Architecture: http://vlsicad.ucsd.edu/Yarchitecture/ , LSI Logic patents • Landing pad shapes (isothetic rectangle vs.. octagon vs.. circle), different spacings (~1.1x) between diagonal and Manhattan wires, etc. • More exceptions • More non-default classes (timing, EM reliability, …) • Not just power and clock • >0.25um width may be “wide” many exceptions
Symptoms: Routing Rules • Degrade completion rates, runtime efficiency • “Postprocessing” likely no longer suffices • E.g., antennas • There is no chip until the router is done • Must / Should / Can tomorrow’s IC routers “independently” address these issues?
Whose Job Is It To Solve: • Mask NRE cost ( runtimes shapes complexity) • BEOL catastrophic yield loss • Deposited copper can infer yield loss mechanisms • Open faults more prevalent than short or bridging faults • High-resistance via faults • Cf. “non-tree routing” for reliability and yield? • Variability budget for planarization • Copper is soft dual-material polish mechanisms • Oxide erosion and copper dishing cross-sectional variability, inter-layer bridging faults, … • Low-k: thermal properties, anisotropy, nonuniformity • Resistivity at small conductor dimensions
The Problem: Evolution • Conflicting goals • Designer: “freedom”, “reuse”, “migration” • EDA: “maintenance mode” • Process/foundry: “enhance perceived value” (= add rules) • Prisoner’s Dilemma: who will invest in change? • Fiddling: Incremental, linear extrapolation of current trajectory • “GDS-3” • Thin post-processing layers (decompaction, RET insertion, …) • Leads to “dark future” (12th Japan DA Show keynote)
The Solution: Co-Evolution • Designer, EDA, and process communities cooperate and co-evolve to maintain the cost (value) trajectory of Moore’s Law • Must escape Prisoner’s Dilemma • Must be financially viable • At 90nm to 65nm transition, this is a matter of survival for the worldwide semiconductor industry
Today’s Design-Manufacturing Interfaces Design Rules Device Models Library (Library Team) Litho/Process (Tech. Development) Layout & libs (Corner Case Timing) RET Mask: Dataprep (Mask House) Design (ASIC Chip) Layout (collection of polygons ?) Tapeout Guardbanding all the way in all stages!! (e.g. clock ACLV guardband ~ 30%) • What do we lose ? • Performance Too much worst-casing • Turnaround time Huge OPC runtimes, overdesign • Predictability RET is applied post-design • Mask costs Overcorrection • Designer’s intent RET is not driven by design
Foundation of the DFM Solution • Bidirectional design-manufacturing data pipe • Fundamental drivers: cost, value • Pass functional intent to manufacturing flow • Example: RET for predictable timing slack, leakage, yield • RETs should win $$$, reduce performance variation • cost-driven, parametric yield constrained RET • Pass limits of manufacturing flow up to design • Example: avoid corrections that cannot be manufactured or verified e.g., design should be aware of metrology N.B.: 1998-2003 papers/tutorials: http://vlsicad.ucsd.edu/~abk/TALKS/
This Tutorial • Concrete examples of Manufacturing-Driven PD • Deployable today • Topic 1: Composability: PSM and SRAF • Topic 2: Performance impact limited fill insertion • Topic 3: Function Aware OPC • Topic 4: Library-based OPC for predictability • Topic 5: Focus and proximity-effects aware STA • Some ramblings about future: regular layout, robust optimization, leakage saving without multi-Vt • We will start with a “manufacturing primer” …
Outline • Challenges • “DFM Philosophy” • Manufacturing and Variability Primer • Lithography, Masks and Process Variations • Design for Value • Composability • Performance Impact Limited Fill Insertion • Function Aware OPC • Systematic Variation Aware STA • Futures of Mfg-Aware PD
Photo-Lithographic Process optical mask oxidation photoresist photoresist coating removal (ashing) stepper exposure Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process spin, rinse, dry step
Lithography Primer: Basics • The famous Raleigh Equation: : Wavelength of the exposure system NA: Numerical Aperture (sine of the capture angle of the lens, and is a measure of the size of the lens system) k1: process dependent adjustment factor • Exposure = the amount of light or other radiant energy received per unit area of sensitized material. • Depth of Focus (DOF) = a deviation from a defined reference plane wherein the required resolution for photolithography is still achievable. • Process Window = Exposure Latitude vs. DOF plot for given CD tolerance
Numerical Aperture • NA=nsin n=refractive index for air, UB =1. Practical limit ≈ 0.93 • NA increase DOF decrease • Immersion lithography ? n>1 (e.g., water) Figures courtesy www.icknowledge.com
k1 • k1 is complex process depending on RET techniques, photoresist performance, etc • Practical lower limit ≈ 0.25 • Minimum resolvable dimension with 193nm steppers = 0.25*193/0.93 = 52nm Source: www.icknowledge.com
l RET Basics • The light interacting with the mask is a wave • Any wave has certain fundamental properties • Wavelength () • Direction • Amplitude • Phase • RET is wavefront engineering to enhance lithographyby controlling these properties Direction Amplitude Phase Courtesy F. Schellenberg, Mentor Graphics Corp.
or Direction: Illumination • Regular Illumination • Many off-axis designs (OAI) • Annular • Quadrupole / Quasar • Dipole +
130 nm lines, printed at different pitchesQuasar illumination NA=0.7 Acceptable Isolated Unacceptable Dense OAI: Impact on PD • Off axis amplifies certain pitches at the expense of the others “Forbidden” pitches • Quasar / Quadrupole Illumination • Amplifies dense 0°, 90 ° lines • Destroys ±45° lines • Dipole Illumination • Prints only one orientation • Must decompose layout for 2 exposures Depth of Focus Pitch (nm) Graph reference: Socha et al. “Forbidden Pitches for 130 nm lithography and below”, in Optical Microlithography XIII, Proc. SPIE Vol. 4000 (2000), 1140-1155.
Amplitude: OPC • Optical Proximity Correction (OPC)modifies layout to compensate for process distortions • Add non-electrical structures to layout to control diffraction of light • Rule-based or model-based
Dense CD window Exposure Iso CD window Defocus OPC: Assist Features • SRAF = Sub-Resolution Assist Feature ≡ SB = Scattering Bar ≡ Assists • SRAFs make isolated lines “behave” as dense • SRAF are not supposed to be printed on wafer but exist on mask Process Overlap Window Iso-window after SRAF insertion
Phase shifter Phase: PSM • Phase Shifting Masks (PSM) etch topography into mask • Creates interference fringes on the wafer Interference effects boost contrast Phase Masks can make extremely small gates phase shifting mask conventional mask glass Chrome Electric field at mask Intensity at wafer
0 + = 180 180 Double-Exposure Bright-Field PSM
shifters The Phase Assignment Problem • Assign 0, 180 phase regions such that critical features with width < B are induced by adjacent phase regions with opposite phases 0 180 <B
Key: Global 2-Colorability • Odd cycle of “phase implications” ® layout cannot be manufactured • layout verification becomes a global, not local, issue ? 180 0 180 180 0 180
Phase Assignment for Bright-Field PSM • PROPER Phase Assignment: • Opposite phases for opposite shifters • Samephase for overlapping shifters Overlapping shifters
Critical features: F1,F2,F3,F4 F2 F4 F1 F3
F2 F4 F1 F3 Opposite-Phase Shifters (0,180)
S3 F2 S4 S8 F4 S7 S1 F1 S2 S5 F3 S6 Shifters: S1-S8 PROPER Phase Assignment: • Opposite phases for opposite shifters • Same phase for overlapping shifters
Phase Conflict S3 F2 S4 S8 F4 S7 S1 F1 S2 S5 F3 S6 Phase Conflict Proper Phase Assignment is IMPOSSIBLE
Conflict Resolution: Shifting S3 F2 S4 S8 F4 S7 S1 F1 S2 S5 F3 S6 Phase Conflict feature shifting to remove overlap
Conflict Resolution: Widening S3 F2 S4 S8 F4 S7 S1 F1 S2 F3 Phase Conflict feature widening to turn conflict into non-conflict
Minimum Perturbation Problem • Layout modifications • feature shifting • feature widening area increase, slowing down manual fixing, design cost increase • Minimum Perturbation Problem: Find min # of layout modifications leading to proper phase assignment. [Kahng et al. ASPDAC 2001]
OPC Fracture Mask Mask Costs(1) Design Mask Cost Data Volume OPC, PSM, Fill increased feature complexity increased mask cost Figure courtesy Synopsys Inc.
Mask Costs(2) Half of all mask sets used for < 570 wafers (< 100K parts) Vector scan: Write cost proportional to feature complexity Difficult to inspect, verify masks!
Manufacturing Yield • IC manufacturing process affected by random disturbances • different silicon dioxide growth rates, mask misalignment, drift of fabrication equipment operation, etc…. • These disturbances are often uncontrollable and affect the circuit performance • Yield: percentage of manufactured products that pass all performance specifications • Parametric yield (process variations) • What is the performance of the manufactured chips? • Catastrophic or functional yield (defects) • How many chips work?
Process Variation Taxonomy • Spatial scale: • Die-to-Die or Inter-Die. E.g. Focus, etch • Within-Die or Intra-Die. E.g. lens aberration, diffraction effects • Nature: • Random. E.g. batch-to-match material variation • Systematic. E.g. diffraction-based proximity effects • Systematic but difficult to model variations random
Process Variation Sources • Wafer: topography, reflectivity • Reticle: CD error, proximity effects, defects • Stepper: Lens heating, focus, dose, lens aberrations • Etch: Power, pressure, flow rate • Resist: Thickness, refractive index • Develop: Time, temperature, rinse • Environment: Humidity, pressure
Simulation of Variation • Value X for a given parameter for a device i in path j in the kth Monte-Carlo run is given by • RAN-WID: Random within-die variation • RAN-DTD: Random die-to-die variation • SYS-WID: Systematic within-die variation • SYS-DTD can not be accounted for at die-scale