Understanding the 6-stage Typical Pipeline in Scalar Pipelined Processors
This session focuses on the operation of the 6-stage typical pipeline in scalar pipelined processors, detailing the interface between memory subsystems and the register file. Topics will cover various stages including instruction fetching (IF), instruction decoding (ID), executing (EX), and memory access (MEM) to write back (WB). We will explore critical concepts such as load forwarding, interlocks, execution penalties, and performance optimization to achieve a Cycle Per Instruction (CPI) of 1. The session will also discuss the implications for processor performance as illustrated by benchmarks across microprocessor families.
Understanding the 6-stage Typical Pipeline in Scalar Pipelined Processors
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Presentation Transcript
The 6-stage TYPICAL pipeline: Scalar Pipelined Processors
Pipeline Interface to Register File: add R1 <= R2 + R3 x0246 1 2 3 x0123 x0123
6-stage TYP Pipeline load R3 <= M[R4 + R5] x99 x84 3 4 5 x80 x04 +
IF ID RD R1 R1 i+1: i+2: i+3: R1 b a c ALU i+2: R1 R1 i: R1 i+1: ALU i+1: i: R1 MEM FORWARDING PATHS i: R1 WB (i i+1) (i i+2) (i i+3) Forwarding Forwarding i writes R1 before i+3 via Path b via Path a reads R1 ALU Interlock and Penalty
IF ID RD i+1: R1 R1 i+2: i+1: R1 e d ALU i+1: R1 LOAD i:R1 MEM[] FORWARDING PATH(s) MEM i:R1 MEM[] WB i:R1 MEM[] (i i+2) (i i+1) (i i+1) i writes R1 Stall i+1 Forwarding before i+2 via Path d reads R1 Load Interlock and Penalty
• • Register File • • • • • Comp Comp Comp Comp 1 0 1 0 1 0 1 0 • 1 0 1 0 ALU ALU • • Load Forwarding Path • A d d r D-Cache D a • t a • LOADWB • • LoadMEM Stall IF,ID,RD,ALU
IF ID RD ALU BRANCH PENALTY ALU PENALTY MEM LOAD PENALTY WB 3 Major Penalty Loops of Pipelining Performance Objective: Reduce CPI to 1.
IPC x GHz Processor Performance = ----------------- inst. count “Iron Law” of Processor Performance Time 1/ProcessorPerformance = --------------- Program Cycles Time Instructions = ------------------ X ---------------- X ------------ Instruction Program Cycle (inst. count) (CPI) (cycle time)
