Redefining the FPGA

1. Redefining the FPGA

2. Cache Memory Custom Logic Translators Clock Mgmt Processor SDRAM Old FPGA Old FPGA Backplane Logic Glue Logic Virtex as a System Component 100MHz System Performance 2x CLK 1x CLK SSTL3 LVCMOS 2x CLK LVTTL 1M Gates GTL+

3. 10M 2M 1M 500k 250k 180k Density Leadership 10M Gates In 2002 Virtex II Density (system gates) One million gates available today Virtex XCV1000 XC40250XV XC40125XV XC4085XL 1997 1998 1999 2000 2002 Virtex Spans 50K to 1 Million System Gates

4. Virtex Provides Quantum Leapin FPGA Performance I/O Performance Virtex SelectIO 200MHz 200 Virtex Internal Logic Performance 100MHz 100 Performance (MHz) Other FPGAs 50 Reg I/O 4x Increase in I/O Performance Simple I/O 90 94 98 99 Year

5. Virtex ClockSync DLLs Allow 200MHz System Performance Deskew Clocks on Board DLL1 DLL2 Deskew Clocks on Chip Cascade DLLs Manage up to 4 System Clocks Convert Clock Levels using SelectI/O DLL3 DLL4 Generate Clocks -multiply -divide -shift 4 DLLs in each Virtex Device Delay Locked Loops Synchronize on-chip and board level clocks

6. Chip to Chip LVTTL, LVCMOS Chip to Memory SSTL2-I, SSTL2-II, SSTL3-I, SSTL3-II, HSTL-I, HSTL-III, HSTL-IV, CTT Chip to Backplane PCI66, PCI33-5V, PCI33 3.3V, GTL, GTL+, AGP Future SelectI/O Technology allows support for future standards Virtex Supports 15 I/O Standards SSTL SDRAM HSTL LVTTL LVCMOS CTT SRAM GTL+ Select I/OTM Any standard on any pin Multiple standards simultaneously

7. 3 Level Memory Hierarchy Enables200MHz Bandwidth Virtex On-Chip SelectRAM+TM Memory Large FIFOs Packet Buffers Video Line Buffers Cache Tag Memory Deep/Wide SDRAM ZBT SSRAM SGRAM DSP Coefficients Small FIFOs Shallow/Wide 4Kx1 2Kx2 1Kx4 512x8 256x16 16x1 Distributed RAM Block RAM External RAM megabytes kilobytes bytes 200 MHz Memory Continuum Highest performance FPGA memory system

8. Virtex Software Breaks New Ground • The Industry’s first million gate design capabilities • Highest performance through push button flows • Web enabled design tools (Silicon Xpresso) • SmartIP Technology for high design productivity Available Today in v1.5!

9. MHz 0% 100 100MHz System Performance 25% 75 75% Reduction in Place & Route runtime 50% 50 75% TimingDriven Implementation 25 100% 0 v 1.5 v 1.5 1 Million Gates* Under 5 Hours@ 100 MHz High-speed, predictable performance with Vector Based Interconnect 200K gates/hr

10. DSP ATM 66MHz PCI SmartIP™ Optimized Vector-Based Interconnect Vector Based Interconnect 2ns 2ns 2ns 2ns • Predictable high performance • Optimized for synthesis

11. Virtex IP Availability

12. Virtex IP Availability *Customer demand can drive availability to 1Q99

13. Density Range and Package Leadership

14. Industry Leading Price Points * 6,000 gates per dollar End of 1999 pricing based on 100,000 units

15. Virtex Testimonials AdTech, Inc. "These million gate devices enable our test modules to provide thousands of continuous measurements at telecom speeds up to 2.4 gigabits per second," said Carl Uyehara, vice president of engineering at Adtech, Inc., a leading supplier of broadband test systems. "We especially like the fact that Virtex devices are programmable. This allows us to use a single test module for multiple transmission technologies such as ATM and frame relay, which provides huge cost savings and convenience for our customers plus future enhancement capability.”Carl Uyehara, vice president of Engineering Hughes Space and Communication Company "The critical features of Virtex, such as the segmented routing and 0.22 micron feature size, allowed new levels of performance for our high-speed digital designs. The lower voltage and higher performance logic of the Virtex process are unmatched from any other supplier. The level of support from the design development and the hotline assistance that Xilinx offered with the new family also impressed us.” Ted Pascaru, Senior Staff Engineer News Data Services (NDS) "Virtex FPGAs have allowed us to implement our next generation digital TV broadcast systems in record time. A key time saver was the availability of multiple DLLs that allowed us to synchronize a 74 MHz clock to more than 30 devices including multiple FPGAs, SDRAMs, and other components. Designing a no-skew clock system from scratch would take months. Xilinx delivered a ready-made solution to us with Virtex FPGAs.” John Simmons, Project Manager Nortel Networks "In our next generation networking product, we specifically needed block RAM with true dual-port capabilities. We investigated various programmable solutions available and found that no other vendor could provide a single chip solution containing block memory with the ability to read and write to one port and simultaneously read from the other. Additionally, the Virtex DLLs performance was required in order to interface directly to an ASIC running at 78 MHz. Not only do Virtex devices meet our 78 MHz internal performance requirements, they meet our external interface performance requirements by providing very fast 'clock-to-out' timing on even the slowest device.”Ranvir Chitkara, Director of Engineering

16. Summary • Complete Virtex solution available NOW • Silicon, Software, Cores, Support • Breaks density and performance barriers • 1M Gates, 200 MHz Chip to Chip performance • The Only System Level FPGA solution • Timing, Memory, Interface and Integration • Available at industry leading price points Virtex moves FPGAs from glue to system component